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T e c h n i c a l I n f o r m a t i o n
Central Processing Unit
The server's CPU is found on an add-on CPU card and not on the
motherboard. The system will accept either a single or dual processor
module. The dual module has a 64-bit data bus interface with its own 1-
Mbyte secondary cache; the single module has a 512-Kbyte cache. The
module provides a high-performance symmetric multiprocessing (SMP)
environment in a server system. In SMP, all processors are equal and have
no preassigned tasks. Distributing the processing loads between more
than one processor increases system performance. This is particularly
useful when application demand is low and the I/O request load is high.
In the SMP environment, processors share the same interrupt structure
and access to common memory and I/O channels.
The module's central processing unit incorporates a processor/cache core
subsection for each processor. Each subsection contains an independent
local bus with a Pentium processor, 82498 DX cache controller and eight
82493 DX cache SRAMs. Each subsection's external two-way set
associative write-back cache provides 1 Mbyte of SRAM secondary cache
memory (512 Kbyte for single processor card) for each processor. Each
Pentium processor has separate 8K internal L1 cache cores for code and
data and an internal numeric processor. A Memory Bus Controller (MBC)
and a Data-Path Parity (DPP) interface both cache cores to the
proprietary bus.
The processor module's power-up configuration logic provides the
server's system board with information about its CPU speed, the presence
of numeric coprocessor, cache size, cache line size and snooping policy.
Features
♦
One or two Pentium processors running at 100 MHz
♦
2/3 bus/core speed ratios enabling operation at 66/100 MHz
♦
82498/82493 Intel cache chip set providing:
−
1-Mbyte cache capacity (512 Kbytes for single processor card)
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Zero wait-state for MRU (Most Recently Used) read hit, one
wait-state for LRU (Least Recently Used) read hit
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Zero wait state write hit cycles
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Enhanced Lock Functionality - Cache Based Locking
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PUPGR# (Potentially Upgradeable Write) support for
enhanced performance with ECC (Error Checking and
Correcting) memory.
5-6 OWNER'S HANDBOOK
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