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THE CONTROLLER SELECTOR
The controller selector permits attaching computer-type peripherals to the DATANET-30.
Eight high-speed channels may be connected to the controller selector enabling the transfer
of data to and from the DATANET-30 on a memory interrupt basis. The eight high-speed
channels, numbered 0 through 7, operate on a priority basis, with channel 0 having the highest
priority and channel 7 the lowest.
The controller selector channel priority assignment is;
Channels 0-5
Any combination of;
Single-access disc storage units
Dual-access disc storage unit
Magnetic tape controller
Each disc storage unit controller may have 4 disc storage units.
Each magnetic tape controller may have 8 tape handlers.
DATA COMMUNICATIONS PROCESSOR
Data Flow
The DA'I'ANET-30 is organized on an 18-bit parallel, bus logic arrangement. Figure 4 is a
basic. diagram of the principal internal working units of the communications processor. The
data is transferred from memory to the arithmetic unit or from a working register through
the lower data bus and the Y-register to the arithmetic unit. The Y-register holds the data
while it is being processed by the arithmetic unit. After the data has been processed by the
arithmetic unit, it is sent to the Z drivers, which are a common distribution center for all
data coming from the arithmetic unit and going to a working register, memory, control unit,
or an input/output channel.
The plus, zero, and even flip-flops also connected to the Z drivers
will reflect the branch conditions of any data sent through the Z drivers. For example,
if
a
word coming from memory and going to a working register is plus, non-zero and odd, the branch
conditions would be phis, non-zero, and odd.
If
the data word was all zeros the branch conditions
would be ·plus, zero, and even.
From the Z drivers the data flows along the upper data bus to
a working register, an input/output channel, or to the memory, according to the instruction
currently being executed.
In Figure 5, the buffer selector and controller selector have been added to Figure 4. Data
coming from
a
working register, going to a transmit data line, flows under program control
from a specified register to the lower data bus into the Y-register. From the Y-register the
[IDruu&~~u~ ~@------------
1-7
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