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The Data-Edit has two, three, or four mem-
ories per controller, and transmits in half-duplex
or full-duplex mode at 100 or 1200 bps. Synchronous
transmissions at 2000 or 2400 bps are also possible.
COMMON PERIPHERAL
CONTROLLER
The common peripheral controller is designed
to permit a GE
/
PAC computer to communicate with
the following GE peripherals:
High-speed
line printer
High-speed
card reader
High-speed
card punch
Magnetic tape
subsystem
Disc storage
subsystem
900/
1200 lpm, 136 char. per line,
buffered
900 cpm either binary or Hollerith
300 cpm either binary or Hollerith
Transfer rates of 7, 500-120, 000
char. per sec.
Capacities of 5, 898, 240 to 94. 36
million characters. Transfer rate
.
of 41, 700 or 83, 400 char. per
second
Each common peripheral controller is ex-
pandable from one to four channels, where each
channel interfaces to one of the above-listed sub-
systems. A program controlled switch allows the
computer to switch from one channel to another.
Therefore, only one channel may be in operation at
any given time. Simultaneous operation may be
achieved by using two or more common peripheral
controllers. Up to eight common peripheral con-
trollers may share one direct memory channel.
Features
The common peripheral controller checks for
"
odd
ones"
parity on all characters coming from the
peripheral subsystems and will
generate
parity on
NAME
MEMORY ADDRESS
23
all character transmissions to the peripheral sub-
systems. This is done by hardware in the common
peripheral controller.
All input subsystems respond to a special signal
called the program load signal. When a common
peripheral subsystem is in the "ready" state and it
receives this signal, it will respond by transmitting
one record to the common peripheral controller.
Operation
The common peripheral controller utilizes four
control words in memory. These words are shown
in Figure 7.
The
pointer word is at a dedicated
core location between 318 and 378. This address
word gives the location Y of the first
of
the three
control words.
The common peripheral controller contains the
control, sequencing, buffering, and storage elements
required to perform core memory to device storage
data transfers and vica versa. An OUT instruction
transfers the pointer word to the controller. After
fetching the control words, the common peripheral
controller transmits the proper commands to the
peripheral.
If
data transfer is required, the unit
initiates the data transfer sequence, controls the
data word fetching from (or storage to) core
memory, controls the data transmission, and
terminates the operation when the designated number
of words have been transferred. When terminating
an operation the common peripheral controller
stores 12 bits of status information into the pointer
word location, and generates a ready signal inter-
rupt to the central processor to request more data
or a new instruction.
The common peripheral controllers
also
re-
spond to the ACT (activate interrupt) and the ABT
(abort) instructions, the latter to accomplish
premature termination.
FORMAT
11
0
Pointer Word
(31
8
to 37
8
)
I
STATUS FIELD
I
y
I
30
Command
&
Status
Word (CSW)
Word Count
Word (WCW)
Starting Address
Word (SAW)
y
Y+l
Y+2
•'
23
11
5
0
NOT USED
PERIPHE,RAL DEVICE
PERIPHERAL OP CODE
NO
23
16
15
0
NOT USED
NO
.
OF WORDS
OF
DATA TO BE TRANSFERRED
23
15
0
I
NOT USED
I
STARTING ADDRESS
OF
DATA IN MEMORY
Figure 7
Common Peripheral Control Words
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