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Mnemonic
Ope·rand
Word Times
DEF
I
NES
DEF 1
DEF 2
DEF 3
DEF 4
DEF 5-10
NES 1
NES 2
NES 3-10
Reset receive flag and data buffer.
Reset transmit flag and data register.
Set receive mode (turn carrier off).
Set transmit mode (turn carrier on) and initiate transmission.
Not used.
I
Receive flag set {data register contains a new word).
Transmit flag set {data register is ready for a new word).
Not used.
LDT - Do not use.
SCN - Do not use.
RECEIVE OPERATION
1
1
Assume that the WBC has been put in the receive mode by the program, that the receive flag.
is reset, and that the sending unit is transmitting a continuous stream of marks (the line is in
the idle condition).
The sending unit starts transmitting a 20-bit word. The word is preceded
by a start bit (a space) and followed by a stop bit' (a mark). When the start bit is received, a
clock is started.
The clock is used to time the future sampling of the line. The start bit is
shifted into the shift register.
At regular intervals, the line is sampled and the bit which is
present at sampling time is shifted into the shift register. When the shift register is full, the
20-data bits are automatically transferred into the data register, the receive flag is set, and
the clock is stopped.
The clock will start again and the above process will repeat when the
next start bit is received on the transmission line. As a protection against noise on the trans-
mission line causing the clock to start running, the word ·buffer circuitry requires that the space
condition exist on the line for at least one-half of a bit time to start the clock. Thus, noise of
less duration than one-half of a bit time will have no effect. Since the word buffer will transfer
a word into the data register whether or not the data register and receive flag are reset, the
program must test the receive flag and take the word before another is transferred into the data
register.
When the program takes the word from the data register, the data register and the
receive flag are automatically reset.
The timing diagram (Figure 20) illustrates how a 20-bit word would be received at a WBC:
1.
The DEF 3 instruction puts the WBC into the receive mode.
2.
The DEF 1 instruction resets the receive flag and data buffer.
3.
The receive clock is shown sampling the line every bit period.
[ID&\1f&~~1f CJ~@------------
V-27
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