Appendix 2 Details Of Buffer Memory - Mitsubishi Electric MELSEC-Q Series User Manual

Appendix 2
(1) Input information area (Un\G0 to Un\G15)
The ON/OFF status of the input signal of the slave module is automatically stored.
For a two-point input slave module (address: 10):
Ex.
The two bits from Un\G0.A are occupied for the input signal because the setting address is 10.
Buffer memory
address F
Un\G0 15
Un\G1 31
Un\G2 47
Un\G3 63
Un\G4 79
Un\G5 95
Un\G6 111 110 109 108 107 106 105 104 103 102 101 100
Un\G7 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112
Un\G8 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128
Un\G9 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144
Un\G10 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160
Un\G11 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176
Un\G12
207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192
Un\G13 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208
Un\G14 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224
Un\G15 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240
(2) Output information area (Un\G4096 to Un\G4111)
When the ON/OFF data of the output signal of the slave module is written from the CPU module, the slave
module automatically outputs the signal.
For a two-point output slave module (address: 30):
Ex.
The two bits from Un\G4097.E are occupied for the output signal because the setting address is 30.
Area with the setting
address of 30
Buffer memory
address
F
Un\G4096 15
Un\G4097 31
Un\G4098 47
Un\G4099 63
Un\G4100 79
Un\G4101 95
Un\G4102 111 110 109 108 107 106 105 104 103 102 101 100
Un\G4103 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112
Un\G4104 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128
Un\G4105 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144
Un\G4106 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160
Un\G4107 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176
Un\G4108 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192
Un\G4109 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208
Un\G4110 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224
Un\G4111 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240
104
Details of Buffer Memory
Area with the setting
address of 10
E D C B A 9
14 13 12 11 10 9
30 29 28 27 26 25
46 45 44 43 42 41
62 61 60 59 58 57
78 77 76 75 74 73
94 93 92 91 90 89
E D C B A 9
14 13 12 11 10 9
30 29 28 27 26 25
46 45 44 43 42 41
62 61 60 59 58 57
78 77 76 75 74 73
94 93 92 91 90 89
Bit No.
8 7 6 5 4 3
8 7 6 5 4 3
24 23 22 21 20 19
40 39 38 37 36 35
56 55 54 53 52 51
72 71 70 69 68 67
88 87 86 85 84 83
99
Bit No.
8 7 6 5 4 3
8 7 6 5 4 3
24 22 22 21 20 19
40 39 38 37 36 35
56 55 54 53 52 51
72 71 70 69 68 67
88 87 86 85 84 83
99
(ON: 1, OFF: 0)
2 1 0
2 1 0
18 17 16
34 33 32
50 49 48
66 65 64
82 81 80
98 97 96
Input area
(256 points)
(ON: 1, OFF: 0)
2 1 0
2 1 0
18 17 16
34 33 32
50 49 48
66 65 64
82 81 80
98 97 96
Output area
(256 points)