Samsung OFFICESERV 7100 Service Manual page 77

Ethernet Interface
AM79C875KC: Ethernet Interface PHY transceiver
RJ-45 connector
Reset Logic
Power On Reset
−
DS1706 power monitor chip is used. If the power is below 3.0 V, reset is performed.
− It is canceled a certain time after reset signals are generated until the power is
stable after the power is turned on, and properly operates.
WATCH DOG Timer Reset
− Through the OSC internal clock transmitted to CPLD, if CPU does not access a
specific address in CPLD within 5 seconds, board reset is generated.
Manual Reset
−
Detects the reset switch being pressed.
−
Reset switch connects the reset signal in CPLD through DS1706, and the reset
signals are generated in CPU, FLASH ROM, PHY, and STL7065.
© SAMSUNG Electronics Co., Ltd.
OfficeServ 7100 Service Manual
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