Mitsubishi Electric FX3G SERIES Programming Manual page 481

FX /FX /FX Series Programmable Controllers
3G 3U 3UC
Programming Manual - Basic & Applied Instruction Edition
Set item
Input variation (incremental)
*1
S
+20
3
alarm set value
Input variation (decremental)
*1
S
+21
3
alarm set value
Output variation (incremental)
alarm set value
*1
S
+22
3
Output upper limit set value
Output variation (decremental)
alarm set value
*1
S
+23
3
Output lower limit set value
*1 Alarm output
S
+24
3
The setting below is required when the limit cycle method is used (when bit 6 is set to "ON" in the operation setting (ACT)).
PV value threshold
S +25
3
(hysteresis) width (SHPV)
Output value upper limit (ULV)
S
+26
3
Output value lower limit (LLV)
S +27
3
Wait setting from end of tuning
cycle to start of PID control
S
+28
3
(Kw)
*1. +20 to
S
3
(ACT).
Setting Value
0 to 32767
0 to 32767
0 to 32767
−32768 to 32767
0 to 32767
−32768 to 32767
0: Input variation (incremental) is not
exceeded.
bit0
1: Input variation (incremental) is
exceeded.
0: Input variation (decremental) is not
exceeded.
bit1
1: Input variation (decremental) is
exceeded.
0: Output variation (incremental) is not
exceeded.
bit2
1: Output variation (incremental) is
exceeded.
0: Output variation (decremental) is
not exceeded.
bit3
1: Output variation (decremental) is
exceeded.
Set it according to the fluctuation of the
measured value (PV).
Set the maximum value (ULV) of the
output value (MV).
Set the minimum value (LLV) of the
output value (MV).
−50 to 32717%
+24 are occupied when any bit 1, 2 or 5 is set to "1" in
S
3
16 External FX Device – FNC 80 to FNC 89
16.9 FNC 88 – PID / PID Control Loop
Remarks
It is valid when bit 1 is set to "1" in
the operation setting (ACT).
It is valid when bit 1 is set to "1" in
the operation setting (ACT).
It is valid when bit 2 is set to "1" and bit 5 is set to
S
"0" in +1 for the operation setting (ACT).
3
It is valid when bit 2 is set to "0" and bit 5 is set to
S
"1" in +1 for the operation setting (ACT).
3
It is valid when bit 2 is set to "1" and bit 5 is set to
S
"0" in +1 for the operation setting (ACT).
3
It is valid when bit 2 is set to "0" and bit 5 is set to
S
"1" in +1 for the operation setting (ACT).
3
It is valid when bit 1 is set to "1" or bit 2 is set to
"1" in S +1 for the operation setting (ACT).
3
They are occupied when bit 6 is set to "ON (limit
cycle method)" in the operation setting (ACT).
+1 for operation setting
S
3
11
S +1 for
3
S +1 for
3
12
13
14
15
16
17
18
19
20
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