Motorola DSP56156 Manual page 63

WR (Write Enable) - three state, active low output. This output is asserted during
external memory write cycles. When WR is asserted in t1, the data bus pins D0-
D15 become outputs and the DSP puts data on the bus during the leading edge
of t2. When WR is deasserted in t3, the external data has been latched inside
the external device. When WR is asserted, it qualifies the A0-A15 and PS/DS
pins. WR can be connected directly to the WE pin of a static RAM. WR is three-
stated during hardware reset or when the DSP is not bus master.
RD (Read Enable) - three state, active low output. This output is asserted during
external memory read cycles. When RD is asserted in late t0/early t1, the data
bus pins D0-D15 become inputs and an external device is enabled onto the
data bus. When RD is deasserted in t3, the external data has been latched in-
side the DSP. When RD is asserted, it qualifies the A0-A15 and PS/DS pins.
RD can be connected directly to the OE pin of a static RAM or ROM. RD is
three-stated during hardware reset or when the DSP is not bus master.
(Bus Strobe) - three state, active low output. Asserted at the start of a bus
BS
cycle (during t0) and deasserted at the end of the bus cycle (during t2). This pin
provides an "early bus start" signal which can be used as address latch and as
an "early bus end" signal which can be used by an external bus controller. BS
is three-stated during hardware reset and when the DSP is not a bus master.
TA TA (Transfer Acknowledge) - active low input. If there is no external bus ac-
tivity, the TA input is ignored by the DSP. When there is external bus cycle ac-
tivity, TA can be used to insert wait states in the external bus cycle. TA is
sampled on the leading edge of the clock. Any number of wait states from 1 to
infinity may be inserted by using TA. If TA is sampled high on the leading edge
of the clock beginning the bus cycle, the bus cycle will end 2T after the TA has
been sampled low on a leading edge of the clock; if the Bus Control Register
(BCR) value does not program more wait states. The number of wait states is
determined by the TA input or by the Bus Control Register (BCR), whichever is
longer. TA is still sampled during the leading edge of the clock when wait states
are controlled by the BCR value. In that case, TA will have to be sampled low
during the leading edge of the last period of the bus cycle programmed by the
BCR (2T before the end of the bus cycle programmed by the BCR) in order not
to add any wait states. TA should always be deasserted during t3 to be sampled
high by the leading edge of T0. If TA is sampled low (asserted) at the leading
edge of the t0 beginning the bus cycle, and if no wait states are specified in the
BCR register, zero wait states will be inserted in the external bus cycle, regard-
less the status of TA during the leading edge of T2.
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BUS CONTROL (9 PINS)
DSP56156 PIN DESCRIPTIONS MOTOROLA