Serial Control - Sc0X; Ssi Reset And Initialization Procedure - Motorola DSP56156 Manual

DC0-DC4
word
clock
Frame
rate
divider
Figure 8-7 SSIx Frame Sync Generator Functional Block Diagram
8.4.5

Serial Control - SC0x

The function of this pin is determined by the SYNC, FSD0 and FSD1 flags in the CRB. In
Asynchronous mode (SYNC=0), this pin is the transmitter frame sync I/O. For synchro-
nous mode (SYNC=1), this pin is used as a frame sync I/O if bit FSD0 is cleared. If bits
FSD0 and FSD1 are set, this pin is used as an output flag. When configured as an output
flag (FSD0=1; FSD1=1), this pin is controlled by bit OF0 in the CRB and changes synchro-
nously with the first transmitted bit of the data. Control status bit IF0 of the SSI status reg-
ister will update regardless of the SYNC, FSD0 or FSD1 bits in the CRB.
8.5

SSI RESET AND INITIALIZATION PROCEDURE

The SSI is affected by three types of reset:
DSP Reset This reset is generated by either the DSP hardware reset (generated by
asserting the RESET pin) or software reset (generated by executing the
RESET instruction). The DSP reset clears the Port Control Register bits,
8 - 8 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)

SSI RESET AND INITIALIZATION PROCEDURE

SYN=0
RX
control
logic
RX frame
sync in
Frame
FSL, FSI
Sync
Type
TX frame
sync out
TX frame
TX
sync in
control
logic
(FSD1&SYN&FSD0) = 1
F1 in
SYN&FSD0=1
F1 out
FSD1
FSD0 | FSD1
F0 out
SYN&FSD0=1
F0 in
Where & is the logical "and" operator,
Where | is the logical "or" operator
SC1x
SC0x
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