Interface With The Dsp56156 Core Processor; Interface Definition - Motorola DSP56156 Manual

INTERFACE WITH THE DSP56156 CORE PROCESSOR

1µF
600Ω
600Ω
1µF
(to microphone)
+
15µF
VssA
digital Vdd
digital Vss
0.01µF
220µF
+
GND
+5V
Ext. GND Ext. Supply
Figure 6-2 DSP56156 Analog Input and Output Diagram
6.4

INTERFACE WITH THE DSP56156 CORE PROCESSOR

This section discusses the use of each bit in the codec control registers.
6.4.1

Interface Definition

The Σ∆ section is seen from the core as a memory mapped on-chip peripheral. Data mem-
ory locations are used for the receive data register, transmit data register, status register,
and control register. One interrupt vector is assigned to the Σ∆ section.
The A/D section (receive) and the D/A section (transmit) are synchronous; that is, a com-
mon interrupt vector is used by the two sections to notify the DSP core that an input sam-
ple is to be read and/or that an output sample is to be written.
MOTOROLA
Vref
Mic
Vref
VddA
0.001µF
Aux
0.001µF
VssA
Bias
R
10KΩ
Bias
Vref
(≤ ±1mA)
0.1µF
54KΩ
Vdiv
≥10 µF
36KΩ
Spkp
≤50nF
≥1KΩ
Spkm
VddA
Single trace
15µF
Single trace
DSP56156 ON-CHIP SIGMA/DELTA CODEC
INS bit
-6dB
6dB
17dB
2.0V ±10%
(2/5 Vdd)
3 POLE
2 ZERO
LPF
VC3-VC0
VssA
+
0.1µF
Analog Decoupling
VssA
near DSP
MGS1-0 bits
Σ∆
modulator
+5dB
6 - 5