Figure 5–54: BREAKER FAILURE 3-POLE [TIMERS] (Sheet 2 of 2) ............................................................................................ 5-111

Figure 5–55: INVERSE TIME UNDERVOLTAGE CURVES........................................................................................................... 5-112

Figure 5–56: PHASE UV1 SCHEME LOGIC .................................................................................................................................. 5-113

Figure 5–57: PHASE OV1 SCHEME LOGIC .................................................................................................................................. 5-114

Figure 5–58: NEUTRAL OVERVOLTAGE SCHEME LOGIC ......................................................................................................... 5-115

Figure 5–59: AUXILIARY UNDERVOLTAGE SCHEME LOGIC..................................................................................................... 5-116

Figure 5–60: AUXILIARY OVERVOLTAGE SCHEME LOGIC ....................................................................................................... 5-117

Figure 5–61: DISTURBANCE DETECTOR SCHEME LOGIC........................................................................................................ 5-119

Figure 5–62: OPEN POLE DETECTOR SCHEME LOGIC............................................................................................................. 5-122

Figure 5–63: 87L TRIP SCHEME LOGIC ....................................................................................................................................... 5-124

Figure 5–64: EXAMPLE FLEXLOGIC™ CONTROL OF A SETTINGS GROUP ............................................................................ 5-125

Figure 5–65: SYNCHROCHECK SCHEME LOGIC........................................................................................................................ 5-129

Figure 5–66: AUTORECLOSURE SCHEME LOGIC (Sheet 1 of 2) ............................................................................................... 5-134

Figure 5–67: AUTORECLOSURE SCHEME LOGIC (Sheet 2 of 2) ............................................................................................... 5-135

Figure 5–68: SINGLE SHOT AUTORECLOSING SEQUENCE - PERMANENT FAULT ............................................................... 5-136

Figure 5–69: DIGITAL ELEMENT SCHEME LOGIC ...................................................................................................................... 5-137

Figure 5–70: TRIP CIRCUIT EXAMPLE 1 ...................................................................................................................................... 5-138

Figure 5–71: TRIP CIRCUIT EXAMPLE 2 ...................................................................................................................................... 5-139

Figure 5–72: DIGITAL COUNTER SCHEME LOGIC...................................................................................................................... 5-141

Figure 5–73: ARCING CURRENT MEASUREMENT ..................................................................................................................... 5-143

Figure 5–74: BREAKER ARCING CURRENT SCHEME LOGIC.................................................................................................... 5-143

Figure 5–75: CONTINUOUS MONITOR SCHEME LOGIC ............................................................................................................ 5-144

Figure 5–76: CT FAILURE DETECTOR SCHEME LOGIC............................................................................................................. 5-146

Figure 5–77: VT FUSE FAIL SCHEME LOGIC............................................................................................................................... 5-147

Figure 5–78: POTT SCHEME LOGIC............................................................................................................................................. 5-150

Figure 5–79: INPUT CONTACT DEBOUNCING MECHANISM AND TIME-STAMPING SAMPLE TIMING .................................. 5-152

Figure 5–80: VIRTUAL INPUTS SCHEME LOGIC ......................................................................................................................... 5-153

Figure 5–81: DIRECT INPUTS/OUTPUTS LOGIC ......................................................................................................................... 5-159

Figure 6–1: FLOW DIRECTION OF SIGNED VALUES FOR WATTS AND VARS ............................................................................ 6-8

Figure 6–2: UR PHASE ANGLE MEASUREMENT CONVENTION ................................................................................................... 6-9

Figure 6–3: ILLUSTRATION OF THE UR CONVENTION FOR SYMMETRICAL COMPONENTS ................................................. 6-10

Figure 6–4: EQUIVALENT SYSTEM FOR FAULT LOCATION ........................................................................................................ 6-18

Figure 6–5: FAULT LOCATOR SCHEME......................................................................................................................................... 6-19

Figure 8–1: CONVENTIONAL RESTRAINT CHARACTERISTIC....................................................................................................... 8-4

Figure 8–2: CONVENTIONAL RESTRAINT CHARACTERISTIC IN TERMS OF PHASORS............................................................ 8-4

Figure 8–3: IMPROVED FAULT COVERAGE OF ADAPTIVE ELLIPTICAL RESTRAINT................................................................. 8-5

Figure 8–4: BLOCK DIAGRAM FOR CLOCK SYNCHRONIZATION IN A 2-TERMINAL SYSTEM ................................................... 8-6

Figure 8–5: ROUND TRIP DELAY & CLOCK OFFSET COMPUTATION FROM TIME STAMPS ................................................... 8-10

Figure 8–6: BLOCK DIAGRAM OF LOOP FILTER........................................................................................................................... 8-11

Figure 8–7: CT SATURATION ADAPTIVE RESTRAINT MULTIPLIER............................................................................................ 8-14

Figure 8–8: 2-TERMINAL TRANSMISSION LINE SINGLE PHASE MODEL FOR COMPENSATION ............................................ 8-15

Figure 8–9: 3-TERMINAL TRANSMISSION LINE SINGLE PHASE MODEL FOR COMPENSATION ............................................ 8-15

Figure 8–10: RESTRAINT CHARACTERISTICS.............................................................................................................................. 8-21

Figure 8–11: SETTINGS IMPACT ON RESTRAINT CHARACTERISTIC ........................................................................................ 8-22

Figure 9–1: TYPICAL HV LINE CONFIGURATION............................................................................................................................ 9-5

Figure 9–2: SAMPLE SERIES COMPENSATED SYSTEM................................................................................................................ 9-8

GE Power Management

L90 Line Differential Relay

F-9

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