Sony BRC-300 Service Manual page 205

[|IC|]
AL440B-24PBF (AVER LOGIC)
4 M (512 k X 8) -BIT FIFO FIELD MEMORY
—TOP VIEW—
INPUTS
DI0 - DI7 : DATA
1 44
IE : INPUT SIGNAL ENABLE
2 43
OE : OUTPUT SIGNAL ENABLE
PLRTY
: ACTIVE POLARITY SELECT
3 42
RCK : READ CLOCK
4 41
RE : READ ENABLE
RESET
: RESET
5 40
RRST : READ ADDRESS RESET
6 39
SCL : SERIAL BUS CLOCK
SDAEN
: SERIAL BUS INTERFACE ENABLE
7 38
TEST : TEST
8 37
WCK : WRITE CLOCK
WE : WRITE ENABLE
9 36
WRST : WRITE ADDRESS RESET
10 35
OUTPUTS
11 34
DO0 - DO7 : DATA
12 33
IRDY : FIFO SPACE AVAILABILITY STATUS
ORDY : FIFO DATA AVAILABILITY STATUS
13 32
14 31
INPUT/OUTPUT
SDA : SERIAL BUS DATA
15 30
16 29
OTHER
NC : NO CONNECTION
17 28
18 27
19 26
20 25
21 24
22 23
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
1 I DI0 12 — GND
2 I DI1 13 I WCK
3 I DI2 14 I WRST
4 I DI3 15 O IRDY
PLRTY
5 — V 16 I
CC
6 I DI4 17 I TEST
7 I DI5 18 — A.V
CC
8 I DI6 19 — NC
9 I DI7 20 — NC
10 I WE 21 — NC
11 I IE 22 — A.GND
INTERNAL
1 - 4,
512 k X 8
WRITE
6 - 9 BUS
8 DATA MEMORY
DI0 - DI7
REGISTER CELL ARRAY
INPUT
BUFFER
MEMORY
CONTROL
15
IRDY
13 TIMING
WCK
GENERATOR
14 INPUT
WRST
CONTROL
11
IE
ARBITER
10
WE
25
REFRESH
SDA
CONTROL
24 COUNTER
SCL
REGISTERS
23
SDAEN
TO ALL MODULES
16 TIMING
PLRTY
AND LOGIC
27
RESET
CONTROL
BRC-300/300P
BRU-300/300P
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
SDAEN
23 I 34 I OE
24 I SCL 35 I RE
25 I/O SDA 36 O DO7
26 — GND 37 O DO6
RESET
27 I 38 O DO5
28 — NC 39 O DO4
29 — V 40 — V
CC CC
30 O ORDY 41 O DO3
31 I RRST 42 O DO2
32 I RCK 43 O DO1
33 — GND 44 O DO0
36 - 39,
INTERNAL
41 - 44
READ
BUS
DATA 8 DO0 - DO7
REGISTER
OUTPUT
BUFFER
30
ORDY
32
RCK
OUTPUT 31
RRST
AND
CONTROL
34
OE
35
RE
DS90CR287MTDX (NS)
CANNEL LINK TRANSMITTER
—TOP VIEW—
INPUTS
TXCLK IN
1 56
TXIN0 - TXIN27
2 55
PWRDOWN
3 54
OUTPUTS
4 53
TXCLK OUT+
5 52
TXCLK OUT_
6 51
TXOUT0+ - TXOUT3+
TXOUT0_ - TXOUT3_
7 50
8 49
OTHERS
9 48
LVDS GND
10 47
LVDS V
CC
PLL GND
11 46
PLL V
CC
12 45
13 44
14 43
51, 52, 54 - 56,
15 42
2 - 4, 6 - 8,
10 - 12, 14 - 16,
16 41
18 - 20, 22 - 25,
27, 28,
17 40
30, 50
TXIN0 - TXIN27
18 39
19 38
20 37
21 36
22 35
31
23 34
TXCLK IN
24 33
25 32
26 31
27 30
28 29
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO. NO.
1 — V 15 I TXIN15
CC
2 I 16 I TXIN16
TXIN5
3 I TXIN6 17 — V
CC
4 I TXIN7 18 I TXIN17
5 — GND 19 I TXIN18
6 I TXIN8 20 I TXIN19
7 I TXIN9 21 — GND
8 I TXIN10 22 I TXIN20
9 — 23 I TXIN21
V
CC
10 I TXIN11 24 I TXIN22
11 I TXIN12 25 I
TXIN23
12 I TXIN13 26 — V
CC
13 — 27 I TXIN24
GND
14 I TXIN14 28 I TXIN25
TXCLK
PREVIOUS CYCLE
TXIN5 _ 1 TXIN27 _ 1
TXOUT3 TXIN23 TXIN17
TXIN20 _ 1 TXIN19 _ 1
TXOUT2 TXIN26 TXIN25
TXIN9 _ 1 TXIN8 _ 1
TXOUT1 TXIN18 TXIN15
TXIN1 _ 1 TXIN0 _ 1
TXOUT0 TXIN7 TXIN6
: TTL LEVEL CLOCK
: TTL LEVEL DATA
: POWER DOWN
: POSITIVE LVDS DIFFERENTIAL CLOCK
: NEGATIVE LVDS DIFFERENTIAL CLOCK
: POSITIVE LVDS DIFFERENTIAL DATA
: NEGATIVE LVDS DIFFERENTIAL DATA
: GROUND FOR LVDS
: POWER SUPPLY FOR LVDS
: GROUND FOR PLL
: POWER SUPPLY FOR PLL
47
TXOUT 0+
48
TXOUT 0_
45
TXOUT 1+
46
TXOUT 1_
41
TXOUT 2+
28
42
TXOUT 2_
37
TXOUT 3+
38
TXOUT 3_
39
TXCLK OUT+
PLL
40
TXCLK OUT_
PIN
I/O SIGNAL I/O SIGNAL
NO.
29 — GND 43 — LDVS GND
30 I TXIN26 44 — LDVS V
CC
31 I TXCLK IN 45 O TXOUT1+
PWRDOWN
32 I 46 O TXOUT1_
33 — PLL GND 47 O TXOUT0+
34 — PLL V 48 O TXOUT0_
CC
35 — PLL GND 49 — LDVS GND
36 — LDVS GND 50 I TXIN27
37 O TXOUT3+ 51 I TXIN0
38 O TXOUT3_ 52 I TXIN1
39 O TXCLKOUT+ 53 — GND
40 O TXCLKOUT_ 54 I TXIN2
41 O TXOUT2+ 55 I TXIN3
42 O TXOUT2_ 56 I TXIN4
NEXT CYCLE
TXIN16 TXIN11 TXIN10 TXIN5
TXIN24 TXIN22 TXIN21 TXIN20
TXIN14 TXIN13 TXIN12 TXIN9
TXIN4 TXIN3 TXIN2 TXIN1
IC
TXIN27
TXIN19
TXIN8
TXIN0
7-3