Table of Contents
Advertisement
21164 Address Space
A.3.1 System Address Map
Figure 1–5 shows the following system address regions:
•
Main memory address space contains 8GB. All transactions contain 64 bytes, are
cache-block aligned, and are placed in cache by the 21164. Both Istream and
Dstream transactions access this address space.
•
PCI sparse-space memory region 1 contains 512MB. Noncached 21164 read/write
transactions are allowed, including byte, word, tribyte, longword (LW), and quad-
word (QW) types. There is no read prefetching.
•
PCI sparse-space memory region 2 contains 128MB.
•
PCI sparse-space memory region 3 contains 64MB.
•
PCI I/O sparse-space memory region A contains 32MB and is not relocatable.
•
PCI I/O sparse-space memory region B contains 32MB and is relocatable by
way of the HAE_IO register.
•
PCI dense memory space contains 4GB for 21164 noncached 21164 transac-
tions. It is used for devices with access granularity greater or equal to a LW.
Read prefetching is allowed, and thus read transactions can have no side effects.
•
The PCI configuration space is used for noncached 21164 access. Sparse-space
read/write transactions are allowed, including byte, word, tribyte, LW, and QW
types. Prefetching of read data is not allowed.
Figure 1–6 shows a detailed view of PCI configuration space that includes 21174
CSRs. The 21174 CSR address space is chosen for hardware convenience.
System Address Space
A–10
Advertisement
Table of Contents
