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Scatter-Gather TLB
Table A–14 Scatter-Gather Mapped PCI Target Address Translation
W_MASK<31:20>
0000 0001 1111
0000 0011 1111
0000 0111 1111
0000 1111 1111
0001 1111 1111
0011 1111 1111
0111 1111 1111
1111 1111 1111
1
Unused bits of the Translated Base Register must be zero for correct operation.
1.15 Scatter-Gather TLB
An eight-entry translation lookaside buffer (TLB) is provided in the 21174 for scat-
ter-gather map entries. The TLB is a fully associative cache and holds the eight
most-recent scatter-gather map lookup PTEs. Four of these entries can be locked to
prevent their being displaced by the hardware TLB-miss handler. Each of the eight
TLB entries holds a PCI address for the tag and four consecutive 8KB 21164 page
addresses as the TLB data, as shown in Figure 1–20.
System Address Space
A–40
Size of SG
Map Table
Translated Address <32:2>
32KB
Translated Base<33:15> : ad<24:13>
64KB
Translated Base<33:16> : ad<25:13>
128KB
Translated Base<33:17> : ad<26:13>
256KB
Translated Base<33:18> : ad<27:13>
512KB
Translated Base<33:19> : ad<28:13>
1MB
Translated Base<33:20> : ad<29:13>
2MB
Translated Base<33:21> : ad<30:13>
4MB
Translated Base<33:22> : ad<31:13>
(Sheet 2 of 2)
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