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•
Hardware does not perform read-ahead (prefetch) transactions in sparse space
because read-ahead transactions may have detrimental side effects.
•
Programmers are required to insert memory barrier (MB) instructions between
sparse-space transactions to prevent collapsing in the 21164 write buffer. How-
ever, this is not always necessary. For example, consecutive sparse-space
addresses will be separated by 32 bytes (and will not be collapsed by the 21164).
•
Programmers are required to insert MB instructions if the sparse-space address
ordering/coherency to a dense-space address is to be maintained.
•
Table 1–6 shows encoding of the 21164 address for sparse-space read transac-
tions to PCI space. An important point to note is that signals addr_h<33:5> are
directly available from the 21164 pins. On read transactions, the 21164 sends out
addr_h<2:0> indirectly on the int4_valid pins. Signals addr_h<2:0> are
required to be zero. Transactions with addr_h<2:0> not equal to zero will pro-
duce UNPREDICTABLE results.
•
Table A–5 shows the relation between int4_valid<3:0> and addr_h<4:3> for a
sparse-space write transaction. Unlisted int4_valid patterns will produce
UNPREDICTABLE results (that is, as a result of collapsing in the 21164 write
buffer; or by issuing a STQ instruction when a STL instruction is required).
Table A–5 Int4_valid and 21164 Address Relationship
EV5 Data Cycle
First
Second
1
All other int4_valid patterns result in UNPREDICTABLE results.
2
Only one valid STQ case is allowed.
PCI Sparse Memory Space
1
Int4_valid<3:0>
00 01
00 10
01 00
10 00
00 01
00 10
01 00
10 00
2
11 00 (STQ)
Address<4:3>
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
1 1
System Address Space
A–19
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