Fujitsu F2MC-8FX Hardware Manual page 83

Standby Mode State Transition Diagram
Figure 6.8-1 and Figure 6.8-2 are standby mode state transition diagrams.
Figure 6.8-1 Standby Mode State Transition Diagram (Two-system Clock Product)
Stop mode
(4)
(6)
(7)
Timebase
timer mode
<2>
Main clock oscillation
stabilization wait time
(3)
Main clock/main
PLL clock
Subclock oscillation
stabilization wait
time
Main PLL clock
oscillation stabiliza-
tion wait time
Power on
Reset state
Reset occurs in each state.
<1>
(8)
Normal
(RUN) state
(5)
(1)
(2)
Sleep mode
CHAPTER 6 CLOCK CONTROLLER
Watch mode
(9)
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