Fujitsu F2MC-8FX Hardware Manual page 370

CHAPTER 20 UART/SIO
When the use of the external clock signal has been set, serial data transmission starts at the fall of the first
serial clock signal after the transmission process is started.
A transmission completion interrupt occurs the moment the transmit data register empty (TDRE) bit is set
to "1" when the transmission interrupt enable bit (TIE) contains "1". At this time, the next piece of transmit
data can be written to the UART/SIO serial output data register (TDR0). Serial transmission can be
continued with the transmission operation enable bit (TXE) set to "1".
To use a transmission completion interrupt to detect the completion of serial transmission, enable
transmission completion interrupt output this way: TEIE = 0, TCIE = 1. Upon completion of transmission,
the transmission completion flag (TCPL) is set to 1 and a transmission completion interrupt occurs.
Writing
to TDR0
UCK
UI
TDRE
TCPL
Concurrent transmission and reception
<When external clock is enabled>
Transmission and reception can be performed independently of each other. Transmission and reception
can therefore be performed at the same time or even when their phases are shifted from each other and
overlapping.
<When internal clock is enabled>
As the transmitting side generates a serial clock, reception is influenced.
If transmission stops during reception, the receiving side is suspended. It resumes reception when the
transmitting side is restarted.
• Operation with serial clock output
Refer to "20.4 Pins of UART/SIO".
• Operation with serial clock input
Refer to "20.4 Pins of UART/SIO".
356
Figure 20.7-14 8-bit Transmission in Synchronous CLK Mode
D0 D1 D2 D3 D4 D5 D6 D7
Interrupt
After falling of UCK
when external clock
to interrupt
is enabled.
controller
Interrupt
After last 1-bit cycle
when internal clock
to interrupt
is enabled.
controller