Interrupts Of Watch Counter - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 14 WATCH COUNTER
14.4

Interrupts of Watch Counter

The watch counter outputs interrupt requests when the counter underflows (counter
value = "000001 ").
B
Interrupts of Watch Counter
When the counter of the watch counter underflows, the interrupt request flag bit (WCFLG) of the watch
counter control register (WCSR) is set to "1". If the interrupt request enable bit (ISEL) of the watch counter
is set to "1", an interrupt request of the watch counter is outputted to the interrupt controller.
Table 14.4-1 shows the interrupt control bits and interrupt sources of the watch counter.
Table 14.4-1 Interrupt Control Bits and Interrupt Sources of Watch Timer
Interrupt request flag bit
Interrupt request enable bit
Interrupt source
Register and Vector Table Related to Interrupts of Watch Counter
Table 14.4-2 Register and Vector Table Related to Interrupts of Watch Counter
Interrupt
source
Watch counter*
CHAPTER 8 INTERRUPTS describes the interrupt request numbers and vector tables of all peripheral
functions.
*: The watch counter shares the same interrupt request number and vector table as the watch prescaler.
214
Item
WCFLG bit of the WCSR register
ISEL bit of the WCSR register
Counter underflow
Interrupt level setup register
Interrupt
request No.
IRQ20
Description
Register Setting bit
ILR5 L20
Vector table address
Upper Lower
FFD2 FFD3
H H