Operation Of The Real Time Clock - Fujitsu F2MC-8FX Hardware Manual

27.5

Operation of the Real Time Clock

The operation of the real time clock is described in this section.
Setting time and date
All registers and counters can be written even when they are updating. However, when counter(s) is/are
written, the counter value(s) is/are still updating. Therefore, written data may be altered right after it is
written. In order to set the time and date information properly. User is advised to set the pause bit
(RTCCRL:PAU) to "1" before setting. It can halt the one-second tick. After setting, RTCCRL:PAU can be
set "0" so as to resume the one-second tick.
For setting after power-on, user is strongly recommended to follow the following sequence:
1) Writing "0" to RTCCRH:PS
2) Writing "1" to RTCCRL:PAU
3) Writing data to SECR/MINR/HOUR/DOWR/DAYR/MONR/YEAR/FTTR
4) Writing "0" to RTCCRL:PAU
When the real time clock is in power save mode (writing "1" to RTCCRL:PS), all the counters and registers
cannot be written.
Reading current time and date
When the counter latch bit (RTCCRL:CL) is changed from "0" to "1", all counters's values at that moment
will be latched to coreesponding counter registers. When this bit is "1", the latched counter values are kept
and can be read.
When "0" is written to RTCCRL:CL, the content of the latches will be no longer secured. instead, when
this bit is "0", the latched counter values will being altered in line with the counters's values
Steps for transition to and from subclock/timebase timer/watch mode (RTCCRL:PS=1)
Since resource clock must be at least faster than subclock 4 times and this condition cannot be satisfied in
this mode. So we need to set "1" to RTCCRL:PS to meet this condition. The following are the steps for the
user to get into and out of watch/sub-clock run mode.
Transition to subclock/timebase timer/watch mode (RTCCRL:PS=1)
1) Write "1" to RTCCRL:PS
2) Set Standby Control Register (STBC)/System Clock Register (SYCC).
3) Subclock/timebase timer/watch mode can be accessed.
After transition from watch/sub-clock mode
User can write RTCCRL:PS to "0" or "1" which based on user's decision. But the read value of all counter
registers are indeterminate when setting RTCCRL:PS to "1".
CHAPTER 27 REAL TIME CLOCK
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