User Sma Clock - Xilinx VCU110 User Manual

User SMA Clock

[Figure 1-2, callout 15]
The VCU110 evaluation board provides an SMA pair for the user to source a differential
LVDS clock to FPGA U1 Bank 67. USER_SMA_CLOCK_P and USER_SMA_CLOCK_N are
connected to XCVU190 FPGA U1 (V
respectively. A 100Ω differential termination resistor is present on the board for these
inputs.
The SMA input circuit is shown in
X-Ref Target - Figure 1-13
2
3
4
5
2
3
4
5
GND
VCU110 Evaluation Board
UG1073 (v1.2) March 26, 2016
CCO
Figure
J34
GND1
GND2
1
SIG
GND3
R1448
GND4
100
1
1/10W
32K10K-400L5
1%
J35
2
GND1
GND2
1
SIG
GND3
GND4
32K10K-400L5
Figure 1-13: VCU110 User SMA Clock
www.xilinx.com
Chapter 1: VCU110 Evaluation Board Features
1.5V) HP Bank 67 GC pins AY27 and AY28,
1-13.
USER_SMA_CLOCK_P
USER_SMA_CLOCK_N
45
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