User Sma Clock Source - Xilinx ZC706 User Manual

The user clock circuit is shown in
X-Ref Target - Figure 1-12
See the Silicon Labs Si570 data sheet

User SMA Clock Source

The ZC706 board provides a pair of SMAs for differential user clock input into PL Bank 9 (see
Figure 1-13). The P-side SMA J67 signal USER_SMA_CLOCK_P is connected to U1 pin AD18,
with the N-side SMA J68 signal USER_SMA_CLOCK_N connected to U1 pin AD19. Bank 9
Vcco is VADJ_FPGA, a variable voltage (1.8V, 2.5V, 3.3V) depending on the ZC706 FMC
interface banks voltage. The USER_SMA_CLOCK input voltage swing should not exceed the
board VADJ_FPGA voltage setting.
X-Ref Target - Figure 1-13
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
Figure
VCC3V3
1
U37
R37
Si570
4.7KΩ
2
1/10W
Programmable
5%
Oscillator
1
NC
2
OE
7
USRCLK SFP SDA
SDA
OUT_B-
8
USRCLK SFP SCL
SCL
3
GND
10 MHz-810 MHz
50PPM
GND
Figure 1-12: User Clock Source
[Ref
Figure 1-13: User SMA Clock
www.xilinx.com
1-12.
VCC3V3
1
C348
0.01 μF 25V
X7R
2
6
VDD
GND
1
R323
5
100Ω
1/20W 5%
4
2
OUT+
21].
UG954_c1_13_041113
Feature Descriptions
USRCLK N
USRCLK P
UG954_c1_12_041113
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