Bit Format - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

13.4.8 Bit format

The format of the bits constituting an IEBus communication frame is shown below:
Logic '1'
Logic '0'
Preparation
period
Logic '1': voltage difference between inter-bus wires (BUS+ and BUS-)is below 20 mV (low level)
Logic '0': voltage difference between inter-bus wires (BUS+ and BUS-) is above 120 mV (high level)
Preparation period: First low-level period (logic '1')
Synchronization period: Next high-level period (logic '0')
Data period: Period indicating bit value (logic '1' = low level, logic'0' = high level)
The length of synchronization period and data period are almost the same.
The IEBus establishes synchronization for each bit. The specifications of the time of the entire bit and the
time of the period assigned to the bit differ depending on the type of the transmit bit, and whether the unit
is master or slave.
Moreover, the specified interval for every period (preparation, synchronization, data) in the communication
are detected by both the master and slave. If data cannot be detected within that specified interval, timing
error occurs in both master and slave, and then the communication ends and goes into standby mode.
MB90580 Series
Synchronizatio Data
n
period
period
13.4 IEBus Communication Protocol
Pause Synchronizatio
n
period
period
Data
period
Chapter 13: IE Bus 173