Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 18

Table 7.3a
Table 7.4.3a
Table 7.6.2a
Table 7.6.2b
Table 7.6.2c
Table 7.6.4a
Table 7.6.4b
Chapter 8 Parallel Ports .................................................................................................................................101
Chapter 9 DTP/External Interrupt ..................................................................................................................109
Chapter 10 Delayed Interrupt Generation Module .......................................................................................117
Chapter 11 Communication Prescaler ..........................................................................................................119
Chapter 12 UART ............................................................................................................................................123
Table 12.4.1a UART operation modes ............................................................................................132
Table 12.4.2a Baud rate (f indicates the machine clock.) ................................................................132
Table 12.4.2b Baud rates and reload values ...................................................................................133
Chapter 13 IE Bus ...........................................................................................................................................141
Table 13.3.1a Transmission mode ..................................................................................................146
Table 13.3.1b Setting for GOTM and GOTS ...................................................................................147
Table 13.3.2a Interval for the occurrence of data transmit interrupt ................................................148
Table 13.3.2b Interval for the occurrence of data transmit interrupt ................................................148
Table 13.3.2c Interval for the occurrence of data transmit interrupt ................................................148
Table 13.3.2d Internal clock frequency ............................................................................................149
Table 13.3.5a Control bits setting ....................................................................................................151
Table 13.3.6a Number of transmit data bytes setting ......................................................................152
Table 13.3.8a Status flag .................................................................................................................156
Table 13.3.13a Time Required for next data receive after receive buffer full interrupt occurred ......161
Table 13.3.14a Data write time after WDB empty interrupt ...............................................................162
Table 13.4.1a IEBus transfer rates ..................................................................................................163
Table 13.4.3a Transfer rate and maximum number of transfer byte in each communication mode 164
Table 13.4.6a Number of transmit data bytes setting ......................................................................167
Table 13.4.7a Control bits setting ....................................................................................................170
Table 13.4.7b The control command that can be executed by a locked slave unit .........................170
Table 13.4.7c Meaning of Slave Status ...........................................................................................171
Table 13.5.1a Time required to write transmit data to WDB after transmit interrupt has occurred .175
Table 13.5.2a Meaning of status code ST3-0 for master, slave transmit ........................................177
Table 13.5.2b Meaning of status code ST3-0 for master receive ....................................................177
Table 13.5.2c Meaning of status code ST3-0 for slave receive .......................................................178
Table 13.5.2d Meaning of status code ST3-0 for multiaddress receive ...........................................178
Chapter 14 8/16-Bit PPG ................................................................................................................................191
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MB90580 interrupt assignment table (1/2) ..................................................................83
Compensation values for interrupt processing cycle count ........................................86
ICS bits, channel numbers, and descriptor addresses ...............................................92
S bits and end conditions ............................................................................................92
Interrupt level setting bits and interrupt levels ............................................................93
Execution time when the extended I2OS continues ...................................................99
Data transfer compensation values for extended I2OS execution time ......................99
MB90580 Series