Figure C.3A Timing Of Rdyint And Rdy - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

C.3 Flash Control Register (FMCS)
[bit 4] RDY (ReaDY)
This bit is used to indicate whether the flash memory is ready for programming/erasing. When this bit is set
to "0", programming or erasing the flash memory is not allowed. However, it is possible to issue read/reset
command and sector erase suspend command when this bit is "0".
RDY
0 Programming/erasing is operating
1 Programming/erasing is completed (next data programming/erasing is enabled.
[bit 3] Reserved bit
This bit is reserved. It is recommended to always set this bit to "0" during normal operation.
[bit 0] Reserved bit
This bit is reserved. It is recommended to always set this bit to "0" during normal operation.
[bit 2, 0] LPM1, LPM0 (Low Power Mode)
When accessing flash memory, these two bits are used to control the power consumption of the flash
memory. This bit cannot be set to "00". After reset, these bit must be set to "01", "10" or "11". Since the
flash memory access time by the CPU will be changed according to the frequency of the operating clock, it
is recommended to set these bit according to the operating clock frequency of the CPU.
LMP0
0
0
1
1
Note: RDYINT bit and RDY bit cannot be changed in the same time. Either one of these two bits should
be changed when writing the control software.
Automatic program
algorithm is completed
360 Appendix C: The Flash Memory in the MB90F583
LMP1
0 Initial value (Access prohibited)
1 Low power mode (Internal operation frequency < 4 MHz)
0 Low power mode (Internal operation frequency < 8 MHz)
1 Low power mode (Internal operation frequency < 16 MHz)
RDYINT bit
RDY bit

Figure C.3a Timing of RDYINT and RDY

Ready
Low Power Mode
1 machine cycle
MB90580 Series