Primary Mode - Huawei MU509 Series Hardware Manual

HUAWEI MU509 Series HSDPA LGA Module
Hardware Guide
Table 3-12 Signals on the digital audio interface
Pin No.
5
6
7
8
The MU509 PCM interface enables communication with an external codec to support
linear and μ-law format. The PCM_SYNC runs at 8 kHz with a 50% duty cycle.
Figure 3-22 Circuit diagram of the interface of the PCM (MU509 is used as PCM master)

3.8.3 Primary Mode

On Primary mode MU509 provides a 16-bit linear or μ-law, with short-sync and 2.048
MHz clock (on the PCM_CLOCK pin).
Issue 09 (2014-03-06)
Pin Name
PCM_SYNC
PCM_DIN
PCM_DOUT
PCM_CLK
 PCM_SYNC: Output when PCM master.
PCM_CLK: Output when PCM master.

 It is recommended that a TVS be used on the related interface, to prevent electrostatic
discharge and protect integrated circuit (IC) components.
 Data only edition does not support the voice function.
 The MU509 module only works on primary master mode, PCM_CLK and PCM_SYNC pins
are in the output status.
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Copyright © Huawei Technologies Co., Ltd.
Description of the Application Interfaces
I/O Description
O PCM interface sync
I PCM I/F data in
O PCM I/F data out
O PCM interface clock
DC Characteristics (V)
Min. Typ. Max.
–0.3
2.6 2.9
–0.3
2.6 2.9
–0.3
2.6 2.9
–0.3
2.6 2.9
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