Appendix A: Master Constraints File Listing; Overview - Xilinx VCU1525 User Manual

Master Constraints File Listing

Overview

The master Xilinx® design constraints (XDC) file template for the VCU1525 board provides
for designs targeting the VCU1525 reconfigurable acceleration platform. Net names in the
constraints listed correlate with net names on the latest VCU1525 board schematic. You
must identify the appropriate pins and replace the net names with net names in the user
RTL. See the Vivado Design Suite User Guide: Using Constraints (UG903)
information.
For detailed I/O standards information required for a particular interface, see the constraint
files generated by tools such as the memory interface generator (MIG) and the base system
builder (BSB).
# CLOCKS
# SYSCLK
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
set_property
# USER_SI570_CLOCK
set_property
set_property
set_property
set_property
# EMMCLK
set_property
set_property
VCU1525 Acceleration Platform User Guide
UG1268 (v1.0) November 13, 2017
PACKAGE_PIN AY38 [get_ports SYSCLK0_300_N];
IOSTANDARD DIFF_SSTL12
PACKAGE_PIN AY37 [get_ports SYSCLK0_300_P];
IOSTANDARD DIFF_SSTL12
PACKAGE_PIN AW19 [get_ports SYSCLK1_300_N];
IOSTANDARD DIFF_SSTL12
PACKAGE_PIN AW20 [get_ports SYSCLK1_300_P];
IOSTANDARD DIFF_SSTL12
PACKAGE_PIN E32 [get_ports SYSCLK2_300_N];
IOSTANDARD DIFF_SSTL12
PACKAGE_PIN F32 [get_ports SYSCLK2_300_P];
IOSTANDARD DIFF_SSTL12
PACKAGE_PIN H16 [get_ports SYSCLK3_300_N];
IOSTANDARD DIFF_SSTL12
PACKAGE_PIN J16 [get_ports SYSCLK3_300_P];
IOSTANDARD DIFF_SSTL12
PACKAGE_PIN AV19 [get_ports USER_SI570_CLOCK_N];
IOSTANDARD LVDS [get_ports USER_SI570_CLOCK_N];
PACKAGE_PIN AU19 [get_ports USER_SI570_CLOCK_P];
IOSTANDARD LVDS [get_ports USER_SI570_CLOCK_P];
PACKAGE_PIN AK13 [get_ports FPGA_CCLK];
IOSTANDARD LVCMOS18
www.xilinx.com
[get_ports SYSCLK0_300_N];
[get_ports SYSCLK0_300_P];
[get_ports SYSCLK1_300_N];
[get_ports SYSCLK1_300_P];
[get_ports SYSCLK2_300_N];
[get_ports SYSCLK2_300_P];
[get_ports SYSCLK3_300_N];
[get_ports SYSCLK3_300_P];
[get_ports FPGA_CCLK];
Appendix A
[Ref 11] for more
47
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