System Clock And Qsfp0 Clock - Xilinx VCU1525 User Manual

System Clock and QSFP0 Clock

[Figure 2-1, callout 10]
The system clock source is a Silicon Labs SI5335A quad clock generator/buffer (U9).
• Clock generator: Silicon Labs SI5335A-B06201-GM
Frequency Plan: FS1, FS0=01
°
Input Type: crystal, input frequency 25MHz
°
Device Operating Mode: Clock Generator Loop bandwidth 1.6MHz
°
CLK0A/0B: 300MHz 1.8V low-voltage differential signaling (LVDS)
°
CLK1A/1B: 156.25MHz 1.8V LVDS
°
CLK2A/2B: 90MHz 1.8V CMOS (output on A only)
°
CLK3A/3B: 33.333MHz 1.8V CMOS (output on A only)
°
• Low phase jitter of 0.7 ps RMS
Two outputs of the SI5335A U9 are used:
• CLK0A/B: The system clock (SYSCLK) is a LVDS 300MHz clock wired to SI53340 (U44)
1-to-4 clock buffer, which drives four AC-coupled versions of the 300-MHz clock into
the clock capable (global clock (GC)) inputs of three DDR4 interface banks (C0: bank 63;
C1, C2: bank 70; C3: bank 72). The DDR4 C1 interface gets its clock from bank 64 (which
is in the same column as the C1 bank 65 Addr/Ctrl interface).
• CLK1A/B: The QSFP0_CLOCK_P/N clock is an AC-coupled LVDS 156.25-MHz clock wired
to QSFP0 interface GTY bank 231 MGTREFCLK1 P/N input pins K11 and K10.
• CLK2A is not used
• CLK3A is not used.
The FPGA connections for each clock are listed in
Listing.
VCU1525 Acceleration Platform User Guide
UG1268 (v1.0) November 13, 2017
Chapter 3: Board Component Descriptions
Appendix A, Master Constraints File
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