Ddr4 Dimm Memory; Quad Spi Flash Memory - Xilinx VCU1525 User Manual

Reconfigurable acceleration platform
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Table 3-1: I/O Bank Voltage Rails (Cont'd)
XCVU9P-L2FSGD2104E
Bank 71
Bank 72
Bank 73
Bank 74

DDR4 DIMM Memory

[Figure
2-1, callout 2, 3, 4, 5]
Four independent dual-rank DDR4 interfaces are available on the VCU1525 board. The
VCU1525 board is populated with four socketed single-rank Micron
MTA18ASF2G72PZ-2G3B1IG or Samsung M393A2K40BB1-CRC 16GB DDR4 UDIMMs. Each
DDR4 is 72-bits wide (64-bits plus support for ECC).
Memory interface-to-FPGA bank assignment is shown in
termination voltages are sourced from four independent TI TPS51200DR regulator circuits.
The detailed connections between the four DDR4 DIMM sockets and the
XCVU9P-L2FSGD2104E FPGA banks are listed in
The VCU1525 DDR4 memory interfaces adhere to the constraints guidelines documented in
the "DDR3/DDR4 Design Guidelines" section of the UltraScale Architecture-Based FPGAs
Memory IP LogiCORE IP Product Guide (PG150)
interfaces are 40 Ω impedance implementations.
For more details about the Micron DDR4 DIMM, see the Micron MTA18ASF2G72PZ-2G3B1IG
data sheet at the Micron website
For more details about the Samsung DDR4 DIMM, see the Samsung M393A2K40BB1-CRC
data sheet at the Samsung website

Quad SPI Flash Memory

[Figure
2-1, callout 6]
Two Quad Serial Peripheral Interface (SPI) flash memory devices of the same type and wired
in parallel are provided on the VCU1525 board (U17 and U58). A field effect transistor (FET)
switch structure (U57 and U61) implements a chip-select enable mechanism, controlled by
the MSP432 board management controller (BMC). Only one Quad SPI device can be
enabled at a time.
VCU1525 Acceleration Platform User Guide
UG1268 (v1.0) November 13, 2017
Power Net Name
Voltage
VCC1V2_TOP
1.2V
VCC1V2_TOP
1.2V
VCC1V2_TOP
1.2V
VCC1V2_TOP
1.2V
[Ref
4].
[Ref
www.xilinx.com
Chapter 3: Board Component Descriptions
Connected To
DDR4_C2 DQ[0:31
DDR4 C3 DQ[64:71], ADDR/CTRL
DDR4_C3 DQ[16:31], DQ[40:55]
DDR4_C3 DQ[0:15], DQ[32:39], DQ[56:63]
Table
Appendix A, Master Constraints File
[Ref
3]. The VCU1525 board DDR4 memory
5].
3-1. The DDR4 0.6V V
TT
Listing.
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