Pci Express Endpoint Connectivity - Xilinx VCU1525 User Manual

Figure 3-10 shows the GTY assignments.
The FPGA connections for each quad are listed in
Listing.
X-Ref Target - Figure 3-11
BANK 224
MGTY_224_0
MGTY_224_1
MGTY_224_2
MGTY_224_3
MGT_224_REFCLK0
MGT_224_REFCLK1
BANK 226
MGTY_226_0
MGTY_226_1
MGTY_226_2
MGTY_226_3
MGT_226_REFCLK0
MGT_226_REFCLK1
BANK 230
MGTY_230_0
MGTY_230_1
MGTY_230_3
MGTY_230_4
MGT_230_REFCLK0
MGT_230_REFCLK1

PCI Express Endpoint Connectivity

[Figure 2-1, PCIe edge connector]
The 16-lane PCI Express edge connector CN1 performs data transfers at the rate of 2.5
giga-transfers per second (GT/s) for Gen1, 5.0 GT/s for Gen2, 8.0 GT/s for Gen3, and 16.0
GT/s for Gen4 applications. The PCIe transmit and receive signal datapaths have a
characteristic impedance of 85 Ω ±10%. The PCIe clock is routed as a 100 Ω differential pair.
The FPGA GTY MGT connections for the 16-lane PCIe connector are listed in
Master Constraints File
VCU1525 Acceleration Platform User Guide
UG1268 (v1.0) November 13, 2017
PEX_TX15/RX15
PEX_TX14/RX14
PEX_TX13/RX13
PEX_TX12/RX12
NC
NC
PEX_TX7/RX7
PEX_TX6/RX6
PEX_TX5/RX5
PEX_TX4/RX4
PEX_REFCLK
NC
QSFP1_TX1/RX1
QSFP2_TX3/RX3
QSFP1_TX3/TX3
QSFP1_TX4/RX4
MGT_S1570_CLOCK1
QSFP1_CLOCK
Figure 3-11: GTY Bank Assignments
Listing.
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Chapter 3: Board Component Descriptions
Appendix A, Master Constraints File
BANK 225
MGTY_225_0 PEX_TX11/RX11
MGTY_225_1 PEX_TX10/RX10
MGTY_225_3 PEX_TX9/RX9
MGTY_225_4 PEX_TX8/RX8
MGT_225_REFCLK0 NC
MGT_225_REFCLK1 NC
BANK 227
MGTY_227_0 PEX_TX3/RX3
MGTY_227_1 PEX_TX2/RX2
MGTY_227_3 PEX_TX1/RX1
MGTY_227_4 PEX_TX0/RX0
MGT_227_REFCLK0 NC
MGT_227_REFCLK1 NC
BANK 231
MGTY_231_0 QSFP0_TX1/RX1
MGTY_231_1 QSFP0_TX2/RX2
MGTY_231_2 QSFP0_TX3/RX3
MGTY_231_3 QSFP0_TX4/RX4
MGT_231_REFCLK0 MGT_SI570_CLOCK0
MGT_231_REFCLK1 QSFP0_CLOCK
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X19969-103017
Appendix A,
31