Clock Generation - Xilinx VCU1525 User Manual

Table 3-3 lists the USB switch circuit connections.
Table 3-3: VCU1525 USB Switch Circuit Connections
TS3USB221RSER U59
Pin Pin Name
1 1D+
2 1D-
3 2D+
4 2D-
6 OE_B
7 D-
8 D+
9 S
J17 USB_VBUS2 present
The FTDI FT4232HQ data sheet is available on the FTDI website
The TS3USB221RSER data sheet is available on the TI website

Clock Generation

[Figure 2-1, callout 10, 11, 12]
The VCU1525 board provides eight clock sources to the XCVU9P-L2FSGD2104E device,
listed in Table
Table 3-4: VCU1525 Board Clock Sources
Clock Name
SYSCLK_300 clock buffer U44 source is SI5335A-B06201-GM U9 output CLK0 (300MHz).
DDR4 C0 I/F 300MHz
DDR4 C1 I/F 300MHz
DDR4 C2 I/F 300MHz
DDR4 C3 I/F 300MHz
QSFP0 CLOCK 156.250MHz
QSFP1 CLOCK 156.250MHz
USER/MGT_SI570_CLOCK buffer U43 source is SI570 U14 (156.250MHz default).
VCU1525 Acceleration Platform User Guide
UG1268 (v1.0) November 13, 2017
Schematic
Net Name
USB1_DP
USB1_DN
USB2_DP
USB2_DN
USB_EN_B
USB_DN
USB_DP
USB_SEL
USB_PRES
3-4.
Clock Ref. Des.
U44 (Q0) Silicon Labs Si53340 3.3V LVDS clock buffer. SYSCLK0_300_P/N
DDR4 C0 I/F bank 63.
U44 (Q1) Silicon Labs Si53340 3.3V LVDS clock buffer. SYSCLK1_300_P/N
GPIO I/F bank 64.
U44 (Q2) Silicon Labs Si53340 3.3V LVDS clock buffer. SYSCLK2_300_P/N
DDR4 C2 I/F bank 70.
U44 (Q3) Silicon Labs Si53340 3.3V LVDS clock buffer. SYSCLK3_300_P/N
DDR4 C3 I/F bank 72.
U9 (CLK1) Silicon Labs Si5335A 1.8 LVDS QSFP0_CLOCK_P/N QSFP0
GTY231 REFCLK1
U12 (CLK1) Silicon Labs Si5335A 1.8 LVDS QSFP1_CLOCK_P/N QSFP1
GTY230 REFCLK1
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Chapter 3: Board Component Descriptions
Connected To
Pin Name
J13.3 D_P
J13.2 D_N
J17.2 2
J17.3 3
U19.52 P9_0
U27.7 DM
U27.8 DP
U19.53 P9_1
U19.24 P10_4
Description
Description
USB J13 DP
USB J13 DN
USB J17 DP
USB J17 DN
U59 USB Switch ENABLE_B
FT4232HQ U27 DN
FT4232HQ U27 DP
U59 USB Switch Port Select
USB J17 pin 1 voltage detection
[Ref 6].
[Ref 8].
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