Usb Jtag Interface - Xilinx VCU1525 User Manual

USB JTAG Interface

[Figure 2-1, callout 7]
The VCU1525 board XCVU9P-L2FSGD2104E FPGA U13 is the only component in the Joint
Test Action Group (JTAG) chain. JTAG configuration is available through the USB-to-JTAG
FTDI FT4232HQ U27 bridge device connected to Micro-AB USB connector J13. The FTDI
JTAG signals are level-shifted through TXBN0304 device U35. The PCIe 16-lane edge
connector CN1 JTAG port is connected in parallel through level-shifter U34. GPIO port 3 of
the U19 MSP432 BMC is also connected through level-shifter U33. Each level-shifter enable
pin is controlled by the BMC to allow only one JTAG connection at a time.
JTAG configuration is allowed at any time regardless of the FPGA mode pin settings.
The JTAG chain block diagram is shown in
X-Ref Target - Figure 3-3
U27
FT4232HQ
J13
USB AB
U19
GPIO
PORT
CONTROLLER
CN1
PCIe EDGE
For more details about the FT4232HQ device, see the FTDI website
VCU1525 Acceleration Platform User Guide
UG1268 (v1.0) November 13, 2017
U35
FT TCK
ADBUS0 A1
FT TDO
ADBUS1 A3
FT TDI
ADBUS2 A2
FT TMS
ADBUS3 A4
FT OE
ADBUS5 OE_B
U33
MSP432
MSP TCK
P3_0 A1
MSP TDI
P3_1 A3
MSP TDO
P3_2 A2
MSP TMS
P3_3 A4
MSP EN
P3_4 OE_B
P10_4
SYSTEM
U34
PEX OE
OE_B
PEX TCK
A5 A1
PEX TDI
A6 A3
PEX TDO
A7 A2
PEX TMS
A8 A4
Figure 3-3: VCU1525 JTAG Chain Block Diagram
www.xilinx.com
Chapter 3: Board Component Descriptions
Figure 3-3.
TXBN0304
TCK
B1
TDI
B3
TDO
B2
TMS
B4
3.3V L/S 1.8V
TXBN0304
TCK
B1
TDI
B3
TDO
B2
TMS
B4
3.3V L/S 1.8V
TXBN0304
TCK
B1
TDI
B3
TDO
B2
TMS
B4
3.3V L/S 1.8V
U13R
XCVU9PFSGD2104
TCK
TDI
BANK 0
TDO
TMS
X19965-103017
[Ref 6].
Send Feedback
19