Honeywell bendis king KLN 94 Maintenance Manual page 36

BENDIX/KING
CR5015 removes its negative cycle before the internal ADC of the Host microprocessor samples
it. Q5021 and R5180 are used to select the bias of the input signal. The bias is currently set to 0V.
4.3.4.2.17 Dimming Pot control
The DIM_POT_SENSE circuitry consist of a 5VREF signal at one input to the pot. The wiper volt-
age is monitored by a non-inverting voltage follower op-amp (U5036) and is passed on to the Host
microprocessor to control backlight intensity.
4.3.4.2.18 Lateral and Vertical Deviation Flags
The LATERAL_DEV_FLAG+ signal goes to its nominal 0.7V state when the Lateral Superflag is
in the active high state. The signal goes to its nominal 0V state when the Lateral Superflag is in
its low state. Resistors R5010 and R5148 work with clamp diode CR5004 to create the proper
voltage levels. The VERTICAL_DEV_FLAG+ output works similarly with the signal's output states
corresponding to those of the Vertical Superflag. Resistor R5015 works with clamp diode CR5021
to create the proper voltage levels.
4.3.4.2.19 Superflag Outputs
The LATERAL_SUPERFLAG output circuit consists mainly of two control lines from U5004, two
diodes (CR5005 and CR5008), an NPN transistor (Q5019), a protection diode (CR5007), and a
drive FET (Q5012) which is turned on when the LATERAL_DEV_FLAG+ is on. To turn on the
LATERAL_DEV_FLAG+, a high is written to either pin 3 or 4 of U5004 which enables Q5019 to
drive Q5012. R5004 provides a load for Q5012 when the LATERAL_SUPERFLAG is not loaded.
CR5007 limits the maximum gate voltage of Q5012 to approximately 6.2VDC. R5161 provides a
feedback output status for the Host microprocessor via U5005. EMI and lightning protection for
the line is provided by the suppressor card and C5129. Operation of the
VERTICAL_SUPERFLAG circuit is functionally identical to the LATERAL_SUPERFLAG except
that only one control signal is required. This is pin 2 of U5004. STEERING_SUPERFLAG is iden-
tical to VERTICAL_SUPERFLAG but is driven by U5013-7.
4.3.4.2.20 +From Outputs
The +FROM flag circuit consists of U5036-D and two control lines from U5004. When the TO_EN
signal line is greater than the FROM_EN line, the +FROM output will be at a negative potential
indicating a "TO" direction. When the FROM_EN is greater than the TO_EN signal line, the
+FROM output will be at a positive potential indicating a "FROM" direction. Either of these signals
when driven high will activate the Lateral Superflag circuitry. When both the TO_EN and the
FROM_EN signals are low, the LATERAL_DEV_FLAG+ will be low. This effectively puts the
+FROM signal at the same voltage level as the +TO output of the KLN 94. EMI protection for this
line is provided by C5207.
4.3.4.2.21 Deviation Outputs
Two deviation outputs are available on the KLN 94: Lateral Deviation and Vertical Deviation. The
operation of each output is functionally identical. U5037-C acts as a filter and level shifter to con-
vert the L_CDI PWM signal to levels acceptable for use with a lateral deviation meter movement..
4.3.4.2.22 Annunciator Outputs
Discrete output data is sent from the Host microprocessor via the serial peripheral bus and latched
into U5013. This device is a serial to parallel shift register.
The KLN 94 provides eight annunciator outputs. Since all are functionally identical, only the WAY-
POINT ANNUNCIATEn line will be described.
When pin 15 of U5013 is high, Q5013-B will be turned on. This will sink current from an external
load. Q5026, R5152, R5017, and R5018 form a current fold-back circuit.
Rev 0, Sept/2000 15599M00.JA
KLN 94
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