Honeywell bendis king KLN 94 Maintenance Manual page 31

BENDIX/KING
During program and erasing of the flash memory devices, a VPP of +5VDC will be supplied to the
VPP signal line by U5003 pin 13 when HW_PGM_EN is pulled high by the U5029 decode logic
device. This is done one of two ways, either when a programming adapter is connected to the
J5102 JTAG port connector or by pressing the CURSOR and ENT keys simultaneously on the
front panel at the time power is applied to the unit. The memory contents of U5017 can then be
altered if GRAPHICS_CODE_CSn is low, PERIPH_RDn is high, and PERIPH_WRn is held low.
4.3.4.2.10 Graphics Volatile Memory
The Graphics microprocessor utilizes four 512kbyte (512k x 8) SRAM devices. One of these vol-
atile SRAMs (U5001, U5006, U5018, or U5025) can be read or written to by the microprocessor
when either GRAPHICS_SRAM1_LOn, GRAPHICS_SRAM1_HIn, GRAPHICS_SRAM2_LOn, or
GRAPHICS_SRAM2_HIn is held low while the other three are high. PERIPH_RDn is held low on
a read command and PERIPH_WRn is held low on a write command. These signals are decoded
in U5038 programmable decode logic device.
4.3.4.2.11 Compact Flash Database Interface
The Compact Flash Database Card is manufactured by an external supplier and programmed with
both the NAV and Terrain Databases. The data passed to/from the Compact Flash Database card
through the I/O Board is controlled by U5039 and U5040 as data buffers and latches as well as
U5038 as the controller for these buffers and latches. To read from the Compact Flash Database
card, the microprocessor asserts GRAPHICS_CF_CSn low, GRAPHICS_RDn low,
GRAPHICS_WRn high, and GRAPHICS_ADSn low which are then decoded within U5038. The
decoder generates CF_CE_Hn, CF_CE_Ln, PERIPH_CF_BUF_En, PERIPH_RDn, and
PERIPH_WRn signals to select the area of the Compact Flash Card that is needed to be read.
4.3.4.2.12 Electronically Programmable Logic Devices.
4.3.4.2.12.1
Programmable logic provides various support circuits needed by the unit. This logic circuitry pri-
marily supports the interfacing requirements of the Host and Graphics microprocessors. Six indi-
vidual EPLDs hold the needed circuitry.
The EPLDs use input logic having voltage requirements similar to industry standard TTL logic.
Output drive voltage is similar to TTL logic also.
4.3.4.2.12.2
GRAPH1, GRAPH2, and GRAPH3 use the GRAPHICS_CLKIN 64MHz clock signal from Y6001
for high speed synchronization of signals. GRAPH3 also uses the 32 MHz GRAPHICS_CLKOUT
signal from the Graphics Microprocessor.
The Graphics logic is spread across three EPLDs identified as GRAPH1 (U5040), GRAPH2
(U5039), and GRAPH3 (U5038) on the schematic. Refer to other sections of this document for a
discussion of specific functions assigned to the Graphics EPLDs. The following paragraphs give
an overview of the functions.
4.3.4.2.12.2.1
This function is needed because the disable times for the SRAM, CODE, DPRAM, and CF devices
are longer than the 386EX's timing spec. Without the buffers, bus contention could occur when a
write cycle follows a read to one of these devices.
Page 4-32
General
Graphics EPLD Interface
Buffering and multiplexing of the Graphics microprocessor data bus, PE-
RIPH bus, and CF_BUS.
15599M00.JA
KLN 94
Rev 0, Sept/2000