Host Processor Address Map - Honeywell bendis king KLN 94 Maintenance Manual

BENDIX/KING
uP Chip Select
CSBOOT*
FC1_CS4*
BG_CS1*
BGACK_CS2*
FC2_CS5*
A20_CS7*
A22_CS9*
A19_CS6*
BR_CS0*
A23_CS10*
FC0_CS3*
A21_CS8*
4.3.4.2.4 Host Flash Memories
The 8Mbit (512k x 16) flash memory (U5010) has a 16 kbyte boot block. This Boot Block is to
ensure that the Boot Software is blocked from any accidental write cycles. For read operations,
MAIN_8M_BOOT_CSn is low, MAIN_RDn is low, and MAIN_WRn is high because of decoding
logic of U5029 and U5041.
During program and erasure, a BDM adapter is connected to J5100. A VPP of +5VDC will be sup-
plied to the Flash VPP when HW_PGM_EN is pulled high by the U5029 PLD. Aternatively, both
the Enter and Cursor keys can be depressed and Program code can be loaded via the Data Load-
er RS-232 interface. Memory contents of U5010 can then be altered.
4.3.4.2.5 Host Non-Volatile Memory
The Host side of MAIN Board contains one 512kbyte (512k x 8) of non-volatile RAM. The non-
volatile RAM U5024 retains its data by applying the battery voltage (VCC_BAT) connected to pin
32 through U5002 pin 2. This will also hold MAIN_SRAM_CSn high to avoid any spurious chip
selects in the power down cycle when the unit is turned off. When powered on, +5V will provide
the required supply voltage to the RAM through U5002. MAIN_SRAM_CS_INn at pin 13 of U5002
controls MAIN_SRAM_CSn.
4.3.4.2.6 Database Interface
The maximum capacity of the Database Flash Memory Chip (U5009) is 4MBytes and is divided
into banks of 64kbyte. To select each of the banks, 6 bank select lines BS(5:0) are decoded with
U5023 using DISCRETE_CS2n, MAIN_DATA_BUS(15:0) and MAIN_WRn.
The MAIN_DB_CSn is used to enable each 64K bank. To support bank crossover, another chip
select line, DBXOVER_CSn (CS2*), is used to address the 2K memory segment following a given
bank. A 6-bit adder in the U5023 PLD implements the crossover. Note that the adding occurs
without any extra programming since the microprocessor's CS2* chip select will automatically ac-
tivate once the 64kbyte address is exceeded.
Rev 0, Sept/2000
Designation Size
ROM_CSn 512K
XROM_CSn 256K
DB_CSn 64K
DBXOVER_CSn 2K
SRAM1_CSn 62K
SRAM2_CSn 112K
PERI_CSn 16K
DPRAM_CSn 2K
DUARTn 2K
DISCRETE_CSn 2K
Not used 2K
Not used 8K
TABLE 4-4 Host Processor Address Map
15599M00.JA
Space
00000-7FFFF
80000-BFFFF
C0000-CFFFF
D0000-D07FF
D0800-DFFFF
E0000-FBFFF
FC000-FFFFF
FC000-FC7FF
FC800-FC80F
FC810
FC811-FCFFF
FD000
FD001
FD002-FD7FF
FD800-FDFFF
FE000-FFFFF
KLN 94
Data
Size,
bits
16
16
8
8
8
8
8
8
8
8
8
8
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