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exceptions 8-8
Idle Line 8-8
Receive Data 8-8
Receive Data with Exception Status 8-8
Timer 8-9
Transmit Data 8-8
GPIO 5-9
GPIO functionality 8-24
I/O signals 8-3
Idle Line Wakeup mode 8-3
individual reset state (PCR = $0) 8-6
initialization 8-6
Inter-processor messages 8-2
interrupts 8-6
Multidrop mode 8-2
operating mode 8-1
Asynchronous 8-1
Synchronous 8-1
programming model 8-9
data registers 8-22
Receive Data (RXD) 8-4
recover synchronization 8-2
reset 8-5
SCI Clock Control Register (SCCR) 8-7
8-19
bit definitions 8-19
Clock Divider (CD) 8-20
Clock Out Divider (COD) 8-19
Clock Prescaler (SCP) 8-19
programming sheet B-30
Receive Clock Mode Source (RCM) 8-19
Transmit Clock Source (TCM) 8-19
SCI Control Register (SCR) 8-7
bit defintions 8-12
Idle Line Interrupt Enable (ILIE) 8-13
programming sheet B-29
Receive with Exception Interrupt Enable
(REIE) 8-12
Receiver Enable (RE) 8-14
Receiver Wakeup Enable (RWU) 8-15
SCI Clock Polarity (SCKP) 8-12
SCI Receive Interrupt Enable (RIE) 8-13
SCI Shift Direction (SSFTD) 8-15
SCI Transmit Interrupt Enable (TIE) 8-13
Send Break (SBK) 8-15
Timer Interrupt Enable (TMIE) 8-13
Timer Interrupt Rate (STIR) 8-12
Transmitter Enable (TE) 8-14
Wakeup Mode Select (WAKE) 8-15
Wired-OR Mode Select (WOMS) 8-14
Word Select (WDS) 8-16
SCI Receive Data Register (SRX) 8-9
SCI Status Register (SSR) 8-9
bit definitions 8-17
,
,
,
8-8
8-9
,
,
,
8-8
8-9
8-12
,
8-22
,
8-17
Framing Error Flag (FE) 8-17
Idle Line Flag (IDLE) 8-18
Overrun Error Flag (OR) 8-18
Parity Error (PE) 8-17
Receive Data Register Full (RDRF) 8-18
Received Bit 8 (R8) 8-17
Transmit Data Register Empty (TDRE) 8-18
Transmitter Empty (TRNE) 8-18
SCI Transmit Data Address Register (STXA) 8-9
SCI Transmit Data Register (STX) 8-9
select wakeup on idle line mode 8-15
Serial Clock (SCLK) 8-4
state after reset 8-5
Synchronous mode 8-2
transmission priority
preamble, break, and data 8-7
transmit and receive shift registers 8-2
Transmit Data (TXD) 8-4
Transmit Data Register (STX or STXA) 8-22
Transmit Data Register (STX) 8-23
Wired-OR mode 8-3
Serial Control 0 (SC00 and SC10) signals 7-4
Serial Control 1 (SC01 and SC11) signals 7-4
Serial Control 2 (SC02 and SC12) signals 7-6
Serial Control Direction 0 (SCD0) bit 7-23
Serial Control Direction 1 (SCD1) bit 7-23
Serial Control Direction 2 (SCD2) bit 7-23
Serial Input Flag 0 (IF0) bit 7-4
Serial Input Flag 1 (IF1) bit 7-29
Serial Output Flag (OF0–OF1) bits 7-18
Serial Output Flag 0 (OF0) bit 7-4
Serial Output Flag 1 (OF1) bit 7-23
Serial Receive Data (SRD) signal 7-3
Serial Transmit Data (STD) signal 7-3
setting timer operating mode 9-4
Shift Direction (SHFD) bit 7-22
signals 2-1
signals, functional groups 2-2
single data strobe mode 2-2
Sixteen-Bit Arithmetic Mode (SA) bit 4-11
Sixteen-Bit Compatibility (SC) mode bit 4-12
Sixteen-bit Compatibility mode 3-6
Size register (SZ) 1-8
software polling 6-6
SRAM, interfacing 1-10
Stack Counter register (SC) 1-8
Stack Extension Enable (SEN) bit 4-15
Stack Extension Overflow Flag (EOV) bit 4-16
Stack Extension Underflow Flag (EUN) bit 4-16
Stack Extension Wrap Flag (WRP) bit 4-15
Stack Extension XY Select (XYS) bit 4-16
Stack Pointer (SP) 1-8
standby mode
Stop 1-5
,
8-21
,
7-29
,
7-23
Index-11
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