Precautions At Power On; Recommended Power On/Off Sequence - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

34.3 Precautions at Power On

Follow the power on/off sequence as shown below:

<ON>: VDDI (internal and PLLVDD) + APIXVD12 → VDDE (external) + APIXVD33 →

DDRVDE (external) + APIXVD12 → Signal

<OFF>: Signal → VDDE (external) → DDRVDE (external) → VDDI (internal and PLLVDD) +

Figure 34-1 Recommended Power On/Off Sequence (1)

There is no limitation on the sequence of power on/off of VDDI, VDDE, and DDRVDE if the

following condition is met. (Figure 34-2)

• Do not apply VDDE and DDRVDE (external) continuously for more than 1 second when VDDI

(internal) is off.

1 sec. or less

Figure 34-2 Recommended Power On/Off Sequence (2)

Perform power on/off for VREF according to the DDR2-SDRAM regulation.

Perform power on/off so that power for PLLVDD (PLL) does not exceed VDDI.

Turn on all power. Turning on only a part of them is prohibited.

CMOS IC becomes unstable immediately after power-on so execute a reset immediately.

Set the reset pins (XTRST and XRST) to Low when power-on.

Input clock to ECLK pin immediately after power-on.

If an external clock signal is used.

1 sec. or less