Fifo Control Register (Urtxfcr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

28.6.6 FIFO control register (URTxFCR)

ch0：FFFE_1000 + 08h ch1：FFFE_2000 + 08h ch2：FFF5_0000 + 08h
Address
ch3：FFF5_1000 + 08h ch4：FFF4_3000 + 08h ch5：FFF4_4000 + 08h
Bit 31 30 29
Name
R/W W W W
Initial value X X X
Bit 15 14 13
Name
R/W W W W
Initial
valu X X X
e
Bit No. Bit name
31:8 Unused
7:6 RCVR1:0
5:4 Unused
3 DMA MODE
2 TxF RST
1 RxF RST
0 Unused
* Bit7:0 = 00h, after reset
28 27 26 25
W W W W
X X X X
12 11 10 9
(Reserved)
W W W W
X X X X
Reserved bit (input "0" at writing)
Reception FIFO's trigger level
00: 1 byte
01: 4 byte
10: 8 byte
11: 14 byte
Reserved bit
DMA transfer mode (mode of XTXRDY and XRXRDY pins)
0: Single transfer mode
1: Demand transfer mode
Note: Please use Demand mode to transfer data from/to the UART. This allows
continous operation, even if the UART fill level is higher than the DMA transfer
size.
Transmission FIFO reset
1: Reset
Reception FIFO reset
1: Reset
Reserved bit
24 23 22 21
(Reserved)
W W W W
X X X X
8 7 6 5
RCVR1 RCVR0 (Reserved)
W W W W
X 0 0 0
Function
20 19 18 17
W W W W
X X X X
4 3 2 1
DMA TxF RxF (Reserv
MODE RST RST
W W W W
0 0 0 0
28-9
16
W
X
0
ed)
W
0