Fujitsu MB86R02 Jade-D Hardware Manual page 222

MB86R02 'Jade-D' Hardware Manual V1.64
Internal clock
MEM_EA[24:1] X
MEM_ED[15:0]
tRADC
MEM_XRD
MEM_XWR[1:0]
MEM_XCS[4/2/0]
MEM_RDY
tRADC = Read address setup cycle
tRACC = Read access cycle
tRIDLC = Read idle cycle
Figure 11-4 Word read access to 16bit low speed device
Internal clock
MEM_EA[24:1]
X
1 cycle
MEM_ED[15:0]
X
MEM_XRD
tWADC
MEM_XWR[1:0]
MEM_XCS[4/2/0]
MEM_RDY
tWADC = write address setup cycle
tWACC = Write access cycle
tWWEC = Write enable cycle
tWIDLC = Write idle cycle
Figure 11-5 Word write access to 16bit low speed device
00
D00
tRACC + Wait1 cycle + tRACC + Wait2 cycle
Wait1 cycle
Min 2 cycles
00
1 cycle
D00
tWWEC
tWACC + Wait1 cycle + tWACC + Wait2 cycle
Wait1 cycle
Min 2 cycles
01
D01
tRADC
Wait2 cycle
Min 2 cycles
01
D01
tWADC
tWWEC
Wait2 cycle
Min 2 cycles
X
tRIDLC
X
1 cycle
tWIDLC
11-15