Fujitsu MB86R02 Jade-D Hardware Manual page 725

MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
No. Name
2-0 CKSEL[2:0]
Description
Specify clock frequency supplying to A/D converter.
CKSEL[2:0] Clock frequency setting
000
B
001
B
010
B
011
B
100
B
101
B
110
B
111
B
This clock is made dividing APB clock (41.5MHz.)
Analog voltage sampling is carried out every 16 cycles of clock set in this register.
Sampling late [samples/sec.]
1/4096
1/1024
1/256
1/64
1/32
1/16
1/8
1/4
0.6K
2.5K
10.1K
40.5K
81.0K
162.0K
324.1K
648.4K
26-9