Pwmx Status Register (Pwmxcr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
25.7.6

PWMx status register (PWMxCR)

This register is to set PWM such as pulse output format and polarity.
Address
Bit 31 30 29
Name
R/W R R R
Initial value 0 0 0
Bit 15 14 13
Name
R/W R R R
Initial value 0 0 0
Bit field
No. Name
31-4 (Reserved)
3 ONESHOT
2-1 (Reserved)
0 POL
ch0：FFF4_1000 + 10
ch1：FFF4_1100 + 10
ch2：FFF4_6000 + 10
ch3：FFF4_6100 + 10
ch4：FFF4_7000 + 10
ch5：FFF4_7100 + 10
ch6：FFF4_8000 + 10
ch7：FFF4_8100 + 10
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
(Reserved)
R R R R
0 0 0 0
Reserved bits.
Write access is ignored. The read value of these bits is always "0".
Pulse output format, either continuous output or one-shot output is set.
0 Continuous output (initial value)
1 One-shot output
Reserved bits.
Write "0" to these bits. Read value of these bits are undefined.
Note:
Writing "1" to these bits is prohibited.
Polarity of the pulse is set.
0 Negative pulse (initial value)
1 Positive pulse
H
H
H
H
H
H
H
H
24 23 22 21
(Reserved)
R R R R
0 0 0 0
8 7 6 5
R R R R
0 0 0 0
Description
20 19 18 17
R R R R
0 0 0 0
4 3 2 1
ONESHOT (Reserved) POL
R R/W R/W R/W R/W
0 0 0 0
25-9
16
R
0
0
0