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MB86R02 'Jade-D' Hardware Manual V1.64
Reset value
Control/Configuration register for evaluation window
Bit 16
EnCoordW0
enable coordinates for window 0
Bit 8
EnSignB
Enable for Signature calculation B
Bit 0
EnSignA
Enable for Signature calculation A
TriggerW0
Register address
BaseAddress + 54
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Field name
R/W
Reset value
Trigger register
Bit 9 - 8
TrigMode
00b=start one generation,cancel cyclic g., 01b=start cyclic generations, 01b= reserved ,11b=reserved
Bit 0
Trigger
generate trigger for signature generation, see TrigMode for used trigger mode
IENW0
Register address
BaseAddress + 58
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
Field name
R/W
Reset value
Interrupt Enable Register
Bit 2
IEnResVal
Interrupt enable (for condition see the relevant status field)
Bit 1
IEnCfgCop
Interrupt enable (for condition see the relevant status field)
Bit 0
IEnDiff
Interrupt enable (for condition see the relevant status field)
InterruptStatusW0
Register address
BaseAddress + 5C
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
Field name
R/W
Reset value
Interrupt status register
Bit
IStsResVal
2
Interrupt status flags, a '1' signifies that the corresponding interrupt condition occurred (even if interrupt is disabled), write '1' clears the
flag, Condition: Result register is valid
Bit
IStsCfgCop
1
Interrupt status flags, a '1' signifies that the corresponding interrupt condition occurred (even if interrupt is disabled), write '1' clears the
flag, Condition: Configuration Registers copied to shadow registers
Bit
IStsDiff
0
Interrupt status flags, a '1' signifies that the corresponding interrupt condition occurred (even if interrupt is disabled), write '1' clears the
flag, Condition: The number of error frames (different actual signature and reference value) is higher than the value configured at
"ErrorThres"
StatusW0
Register address BaseAddress + 60
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18
Field name
R/W
Reset value
status register
Bit 18
Diff_B_B
H
H
H
H
17
R
R
0
0
H
H
0
H
16
15 14 13 12 11
10
9
R
R
R
0
0
0
H
H
H
0
0
H
H
9
8
7 6 5 4 3 2 1
0
TrigMode
Trigger
RW
W
0
0
H
H
2
1
0
IEnResVal
IEnCfgCop IEnDiff
RW
RW
RW
0
0
0
H
H
H
2
1
0
IStsResVal IStsCfgCop IStsDiff
RW
RW
RW
0
0
0
H
H
H
8
7 6 5 4 3 2
1
0
Active Pending
R
RWS
R
R
0
0
0
0
H
H
H
H
21-9
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