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MB86R02 'Jade-D' Hardware Manual V1.64
9.5.6 Holding request cancellation level register (HRCL)
The HRCL register sets the holding request cancellation level.
When the IRQ interrupt source is higher than the interrupt level set in the HRCL register, the holding
request cancellation demand is asserted to the bus master.
Address
FFFF_FE00
Bit
31
30
29
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit
15
14
13
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit field
Number
Name
31-4
-
3-0
HRCL3-0
IRC0:
or FFFE_8000
+ 10
H
H
H
28
27
26
25
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
12
11
10
9
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
It is an unused bit.
The write access is ignored. The read value of these bits is undefined.
Set the holding request cancellation level.
These bits are used to set the IRQ interrupt level to issue the holding request cancellation
demand to bus masters other than ARM and TIC.
The bus request cancellation demand is issued when there is a high interrupt from the IRQ
interrupt at the highest level after IRQ interrupt priority is decided, and the interrupt level is set
to the HRCL register. This demand is asserted by the FIQ source.
•
Interrupt level of HRCL register < Interrupt level after the IRQ priority order of
line interrupt is decided -> Issue of cancel request
•
FIQ interrupt source > Issue of cancel request
This function effects bus masters other than the ARM core and TIC directly. Besides, when
other bus masters when there is no bus master do not wait until this cancel request is input, it
becomes invalid.
This bit is initialized by reset by "1111
IRC1: FFFB_0000
IRC2: FFFB_1000
24
23
22
21
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
8
7
6
5
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
Explanation
".
B
+ 10
H
H
+ 10
H
H
20
19
18
17
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
4
3
2
1
-
HRCL3 HRCL2 HRCL1 HRCL0
R/W
R/W
R/W
R/W
X
1
1
1
16
-
R/W
X
0
R/W
1
9-19
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