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Philips Semiconductors
Volume 1
11.8.1 Master Transmitter mode
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver
(see
initialized as follows:
Table 117: I2CONSET used to initialize Master Transmitter mode
The I
set to logic 1 to enable the I
acknowledge its own slave address or the general call address in the event of another
device becoming master of the bus. In other words, if AA is reset, the I
enter a slave mode. STA, STO, and SI must be reset.
The master transmitter mode may now be entered by setting the STA bit. The I
now test the I
When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status
code in the status register (I2STAT) will be 0x08. This status code is used by the interrupt
service routine to enter the appropriate state service routine that loads I2DAT with the
slave address and the data direction bit (SLA+W). The SI bit in I2CON must then be reset
before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in I2STAT are possible. There are 0x18, 0x20, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1).
The appropriate action to be taken for each of these status codes is detailed in
After a repeated start condition (state 0x10). The I
receiver mode by loading I2DAT with SLA+R).
11.8.2 Master Receiver mode
In the master receiver mode, a number of data bytes are received from a slave transmitter
(see
start condition has been transmitted, the interrupt service routine must load I2DAT with the
7-bit slave address and the data direction bit (SLA+R). The SI bit in I2CON must then be
cleared before the serial transfer can continue.
When the slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in I2STAT are possible. These are 0x40, 0x48, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The
appropriate action to be taken for each of these status codes is detailed in
a repeated start condition (state 0x10), the I
mode by loading I2DAT with SLA+W.
User manual
Figure
29). Before the master transmitter mode can be entered, I2CON must be
Bit
7
6
Symbol
-
I2EN
Value
-
1
2
C rate must also be configured in the I2SCLL and I2SCLH registers. I2EN must be
2
C-bus and generate a start condition as soon as the bus becomes free.
Figure
30). The transfer is initialized as in the master transmitter mode. When the
Rev. 01 — 24 June 2005
5
4
3
STA
STO
SI
0
0
0
2
C block. If the AA bit is reset, the I
2
C block may switch to the master
2
C block may switch to the master transmitter
UM10120
2
Chapter 11: I
C interfaces
2
1
0
AA
-
-
x
-
-
2
C block will not
2
C interface cannot
2
C logic will
Table
Table
121. After
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
120.
124
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