Motorola Digital DNA MSC8101 Technical Data Manual page 62

AC Timings
Figure 2-5 is a graphical representation of Table 2-14.
Note:
Number
Note:
Number
Note:
2-12
REFCLK
T1 T2
REFCLK
T1 T2
REFCLK
T1 T2
Figure 2-5. Internal Tick Spacing for Memory Controller Signals
The UPM machine and GPCM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the internal tick. SDRAM
machine outputs change only on the
Table 2-15. AC Characteristics for SIU Inputs
10 Hold time for all signals after REFCLK rising edge
11 AACK/ARTRY/TA/TEA/DBG/BG/BR setup time before REFCLK rising edge
12 Data bus setup time before REFCLK rising edge
a. Normal mode
b. ECC and parity mode
14 DP setup time before REFCLK rising edge
15 Setup time before REFCLK rising edge for all other signals
Input specifications are measured from the TTL signal level (0.8 or 2.0 V) relative to the REFCLK rising
edge.
Table 2-16. AC Characteristics for SIU Outputs
31 PSDVAL/TEA/TA delay from REFCLK rising edge
32a Address bus/Address attributes/GBL delay from REFCLK rising
edge
32b BADDR delay from REFCLK rising edge
33a Data bus delay from REFCLK rising edge
33b DP delay from REFCLK rising edge
34 Memory controller signals/ALE delay from REFCLK rising edge
35 All other signals delay from REFCLK rising edge
Output specifications are measured from the 1.4 V level of the REFCLK rising edge to the TTL signal level
(0.8 or 2.0 V).
T3 T4
T3 T4
T3 T4
rising edge.
REFCLK
Characteristic
Characteristic
for 1:2, 1:3, 1:4, 1:5, 1:6
for 1:2.5
for 1:3.5
Value Units
0.5 ns
5 ns
4.55 ns
6 ns
6 ns
4 ns
Maximum Minimum Units
9 1.0 ns
8.5 1.0 ns
10 1.0 ns
8.5 1.0 ns
10 1.0 ns
5.5 1.0 ns
6 1.0 ns