Watchdog Timer In Timer Mode - Philips P89LPC938 User Manual

Philips Semiconductors
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
watchdog
oscillator
PCLK
WDCON (A7H)
Fig 49. Watchdog Timer in Watchdog Mode (WDTE = 1).

16.4 Watchdog Timer in Timer mode

Figure 50
WDCON are written to the shadow register after one watchdog clock cycle. A watchdog
underflow will set the WDTOF bit. If IEN0.6 is set, the watchdog underflow is enabled to
cause an interrupt. WDTOF is cleared by writing a logic 0 to this bit in software. When an
underflow occurs, the contents of WDL is reloaded into the down counter and the
watchdog timer immediately begins to count down again.
A feed is necessary to cause WDL to be loaded into the down counter before an underflow
occurs. Incorrect feeds are ignored in this mode.
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
watchdog
oscillator
PCLK
WDCON (A7H)
Fig 50. Watchdog Timer in Timer Mode (WDTE = 0).
User manual
÷32
PRESCALER
PRE2 PRE1
shows the Watchdog Timer in Timer Mode. In this mode, any changes to
÷32
PRESCALER
PRE2 PRE1
Rev. 03 — 7 June 2005
WDL (C1H)
8-BIT DOWN
COUNTER
SHADOW REGISTER
PRE0 - - WDRUN
WDL (C1H)
8-BIT DOWN
COUNTER
SHADOW REGISTER
PRE0 - - WDRUN
UM10119
P89LPC938 User manual
(1)
reset
WDTOF WDCLK
002aaa905
interrupt
WDTOF WDCLK
002aaa939
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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