Pci Host Bridge; Interrupt Controller (Mpic) - Motorola MVME2301 Installation And Use Manual

Block Diagram
3

PCI Host Bridge

Interrupt Controller (MPIC)

3-18
The SNAPHAT battery package is mounted on top of the
M48T59/T559 device. The battery housing is keyed to prevent
reverse insertion.
The clock furnishes seconds, minutes, hours, day, date, month, and
year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and
30-day months are made automatically. The clock generates no
interrupts. Although the M48T59/T559 is an 8-bit device, 8-, 16-,
and 32-bit accesses from the ISA bus to the M48T59/T559 are
supported. Refer to the MVME2300-Series VME Processor Module
Programmer's Reference Guide and to the M48T59/T559 data sheet
for detailed programming and battery life information.
The Raven ASIC provides the bridge function between the MPC60x
bus and the PCI Local Bus. It provides 32 bit addressing and 64 bit
data. 64 bit addressing (dual address cycle) is not supported. The
Raven supports various PowerPC processor external bus
frequencies up to 66MHz and PCI frequencies up to 33MHz.
There are four programmable map decoders for each direction to
provide flexible address mappings between the MPC and the PCI
Local Bus. Refer to the MVME2300-Series VME Processor Module
ProgrammerÕs Reference Guide for additional information and
programming details.
The Raven ASIC provides an MPIC Interrupt Controller to handle
various interrupt sources. The interrupt sources are:
Four MPIC timer interrupts
Processor 0 self interrupt
Memory Error interrupt from the Falcon chipset
Interrupts from all PCI devices