Toshiba TLCS-90 Series Data Book page 290

TOSHIBA
3
TMP90C840
Data for the timer registers TREG4 and TREGS are provided by a 2-byte
data load instruction or two I-byte data load instructions, from the
lower eight bits followed by the upper eight bits.
TREG4 TREGS
Upper a bits Lower 8 bits Upper a bits Lower a bits
FFEIH FFEOH FFE3H FFE2H
Capture registers (CAPl and CAP2)
CAPI and CAP2 are 16-bit registers that hold
up-counter UCI6.
the values of the
Data in the capture registers are read by a 2-byte data load
instruction or two I-byte data load instructions, from the lower eight
bits followed by the upper eight bits.
CAP 1 CAP2
Upper a bits Lower a bits Upper a bits Lower a bits
FFDDH FFDCH FFDFH
FFDEH
4 Capture input control circuit
This circuit controls the timing that the capture registers (CAPI and
CAP2) latch the UC16 up-counter value.
The latch timing is set by the register T4MOD4,3 (CAPM).
o If T4MOD4,3
=
00,
The capture function is disabled. Theese bits are initialized to
this mode by resetting.
o If T4MOD4,3
=
01,
The up-counter value is latched into CAPI at the rising edge of the
TI4 (also used as pal/INTI) input, and into CAP2 at the rising edge
of TIS (also used as P82/INT2) input.
o If T4MOD4,3
=
10,
The up-counter value is latched into CAPI at the rising edge of the
TI4 input, and by CAP2 at its falling edge. Only in this mode, the
interrupt INTI occurs at the falling edge.
o If T4MOD4,3
=
11,
The up-counter value is latched into CAPI at the r1s1ng edge of the
timer flip-flop TFFl, and into CAP2 at its falling edge.
The up-counter value can be also latched into the capture registers by
using software. In this case, the current up-counter value is latched
into CAPI each time
"a"
is written into the T4MODS (CAPIN) register.
MPU90-92