Toshiba TLCS-90 Series Data Book page 245

TOSHIBA
TMP90C840
The interrupt enable flags provided for all interrupt request channels
are assigned to the memory address FFE7H or FFE8H. Setting any of
these flags to "1" enables an interrupt of the respective channel.
These flags are initialized to "0" by resetting.
The micro DMA enable flag also provided for each interrupt request
channel is assigned to the memory address FFE6H or FFE7H. The
interrupt request for each channel is placed in the micro DMA
processing mode by setting this flag to
"I".
This flag is initialized
to
"O~'
(general purpose interrupt processing mode) by resetting.
Fig. 3.3. (9) shows the bit configuration of the interrupt enable
flags and micro DMA enable flags.
Interrupt by Timer 2 (INTT2) and that by
AID
converter (INTAD) use a
common interrupt req uest channel. The interrupt controller firs t
accepts INTT2 after a reset. IN TAD can be used by setting the
"INTT2/INTAD
selection bit" (ADIS: Bit 3 of memory address FFE7H) to
"I".
Attention should be paid to the following three modes having special
circuits:
I
INTO Level mode If INTO is not an edge-based interrupt, the
I
function of Interrupt Request Flip-flop is
1
cancelled. Therefore the interrupt request
1
signal must be held until the interrupt
1
request is acknowledged by the CPU. A change
1
in the mode (between edge and level) automat-
1
1 1
ically clears the interrupt request flag.
1
1--------------------1-----------------------------------------------1
I
INTAD' level mode
I
The Interrupt Req uest FI ip-flop can be cleared
1
1 I
only by resetting or reading the register thatl
1 1
stores
AID
conversion value, and cannot be
1
1 1
cleared by an instruction. A change in the
1
1 I
interrupt source (between INTAD and INTT2)
1
I I
automatically clears the interrupt request
1
1 1
flag.
I
1--------------------1-----------------------------------------------1
I
INTRX level mode
I
The Interrupt Request Flip-flop is cleared
1
1 1
only by resetting or reading the serial
1
I I
channel receiving buffer, and not by an
I
1 1
instruction.
I
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