Toshiba TLCS-90 Series Data Book page 17

TOSHIBA TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
Addre8S~------------~
121
Data Memory
32
31 -R-;;1~;;;'-Ba-;;kl-
24 RBI
23-----------
8 Level Stack
8
(16
byte)
1"R-;;i-;t~-; -B~;k-O-
o
RBO
Internal Data Memory Area
RAM locations 8 - 23 serve a dual role in that they contain the program
counter stack which is a stack 2 bytes wide by 8 levels deep. These
locations store returning addresses from subroutines. If the level of
subroutine nesting is less than the permitted 8, you free up 2 bytes of
RAM for general use for every level of nesting not utilized.
• All 64 (TMP8048A) or 128 (TMP8049A) locations are indirectly
addressable through eitheF of two R&~ Pointer Registers which reside at
RO and R1 of the Register array.
The TMP8048A architecture allows extension of the Data Memory to 256
words.
(3) Input/Output Ports
• The TMP8048A has 27 I/O lines which can be used for either input or
output. These I/O I ines are grouped into 3 ports each having 8
bidirectional lines and 3 "test" inputs which can after program
sequences when tested by conditional jump instructions.
• Ports 1 and 2 are each 8-bits wide and have identical characteristics.
Data written to these ports is statically latched and remains unchanged
unt i 1 rewri t ten. As input ports these lines are non-lat ching, i. e • ,
inputs must be present until read by an input instruction.
• All lines of Ports 1 and 2 are called quasi-bidirectional because of a
special output circuit structure (illustrated in Figure 1). Each line
is continuously pulled to a +SV level through a high impedance
res is t i ve devi ce (SOkohm) wh ich is suffi cient to provide t he source
current for a TTL high level yet can be pulled low by a standard TTL
gate thus allowing the same pin to be used for both input and output.
I n order to speed up the "0" to "1" trans i t ion a low impedance device
(5kohm) is swi t ched in momentari ly whenever a "1" is wr i tt en to 1 ine •
When "0" is written to line a low impedance device overecomes the
pullup and provides TTL current sinking capability.
MCU48-7