Toshiba TLCS-90 Series Data Book page 220

TOSHIBA
TMP90C840
In addition to the above instructions, "DJNZ PC+d" and "DJNZ BC,PC+d"
may be used to control program loops.
"DJNZ PC+d" decrements the contents of the Register B (8-bit) each
time the instruction is executed, and executes a relative jump until
it becomes zero. "DJNZ BC, PC+d" decrement s the contents of the
regis ter pair BC (16- bit), and executes a relat ive jump unt i 1 it
becomes zero.
Appendix A lists the TMP90C840 machine instructions. The table
includes the instruction groups, mnemonics, codes, functions, flag
status and executing time.
The execut ing time can be ca lculated us ing the value in the "T"
column, which denotes the number of states. Time for one state is
eq uiva lent to a time twice as long as the clock osci llat ion cycl e.
For example, if the clock oscillation frequency is 10MHz, the time for
one state is 200 ns.
Execut ing "LD A, r" at the clock frequency of lOMHz requires two
states, and thus takes 200ns x 2
=
400ns for the execution.
Appendix B contains code maps. The TMP90C840 supports I-byte opcode
instructions and 2-byte opcode instructions. The I-byte opcode
instruction is formatted as follows:
LD
A,B Opcode
LD
A,n
Opcode
n
LD HL,mn Opcode n
m
LD
(w) ,n
Opcode
w
n
LDW (w),mn
Opcode
w
n m
JR PC+d
Opcode
d
CALL ran Opcode n
m
MPU90-22